A novel nonvolatile memory based on self-organized quantum dots

A novel nonvolatile memory based on self-organized quantum dots

ARTICLE IN PRESS Microelectronics Journal 40 (2009) 492– 495 Contents lists available at ScienceDirect Microelectronics Journal journal homepage: ww...

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ARTICLE IN PRESS Microelectronics Journal 40 (2009) 492– 495

Contents lists available at ScienceDirect

Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

A novel nonvolatile memory based on self-organized quantum dots A. Marent , M. Geller 1, D. Bimberg ¨t Berlin, Hardenbergstr. 36, 10623 Berlin, Germany ¨ r Festko ¨rperphysik, Technische Universita Institut fu

a r t i c l e in f o

a b s t r a c t

Available online 6 August 2008

A novel type of memory based on self-organized quantum dots (QDs) is presented, which merges the advantages of the most important semiconductor memories, the dynamic random access memory (DRAM) and the Flash. A nonvolatile memory with fast access times ðo10 nsÞ and good endurance (41015 write/erase cycles) as an ultimate solution seems possible. A storage time of 1.6 s at 300 K in InAs=GaAs QDs with an additional Al0:9 Ga0:1 As barrier is demonstrated and a retention time of 106 years is predicted for GaSb QDs in an AlAs matrix. A minimum write time of 6 ns is obtained for InAs/GaAs QDs. This value is already in the order of the access time of a DRAM cell and at the moment limited by the RC low pass of the device. An erase time of milliseconds is shown in first measurements on GaSb=GaAs QDs at 100 K. Faster write/erase times below 1 ns even at room temperature are expected for improved device structures. & 2008 Elsevier Ltd. All rights reserved.

Keywords: Semiconductor quantum dots Semiconductor storage Nonvolatile memory III-V semiconductor

1. Introduction Mainly two different semiconductor memories dominate today’s electronic devices: The dynamic random access memory (DRAM) [1] and the Flash [2,3]. The DRAM is used as the main memory in personal computers, where fast access times ðo20 nsÞ in combination with a good endurance (41015 write/erase cycles) is needed. However, the DRAM is a volatile memory with large power consumption, as the information has to be refreshed within tens of milliseconds. The Flash memory is a nonvolatile memory having a retention time of more than 10 years without power consumption, hence, mainly used in mobile phones, mp3-player, digital cameras, etc. In a Flash memory, a floating gate in a metaloxide semiconductor field-effect transistor (MOSFET) acts as the storage unit, while surrounding SiO2 barriers with an energetic height of 3.2 eV maintain the nonvolatility. These barriers, however, lead to a poor write speed (microseconds) and a bad endurance ðo106 Þ, since hot electrons have to be injected into the gate. Future nonvolatile memories should show better endurance and faster write/read time equal or better than in a dynamic random access memory (DRAM). Phase change memories, ferroelectric or magnetic random access memories [4] are thought to present alternatives, but do not yet provide the desired high write speed. In addition, these concepts—not based on charge storage—are less scalable, which is a big disadvantage for future memory generations [5]. One of the promising options is the use of self-organized materials in future memory devices, especially quantum dots

(QDs) [6] based on III–V materials. Using these nano-objects in a floating gate structure would have lots of advantages over silicon-based structures. QDs can be fabricated by a ‘‘bottom-up approach’’ in a Stranski–Krastanov growth mode, where small islands are formed by self-organization without lithography. A variety of material combinations allow band structure engineering with tunable band-offsets and barriers, in contrast to the fixed SiO2 barriers in nowadays Flash. Memories based on III–V material may overcome the Flash problems [7] and produce a nonvolatile memory which has better endurance and a fast access time below 1 ns, faster than a DRAM cell. In this letter, we present a memory concept based on QDs, which should enable very fast write times ðonsÞ independent of the carrier storage time, e.g., in combination also with a long storage time (410 years). The write time in our concept is limited only by the charge carrier relaxation time from the band edge into the QD states, which is below picoseconds at room temperature [8,9], more than four orders of magnitude faster than the write time of a DRAM cell. We show for InAs QDs with an Al0:9 Ga0:1 As barrier a storage time of seconds at room temperature and propose more than 106 years for GaSb QDs in an AlAs matrix [10]. We present a minimum write time of 6 ns in InAs=GaAs QDs, already in the order of access time of a DRAM cell [11]. The write time is at the moment limited by the RC low pass of the device. An erase time of milliseconds is shown in first measurements on GaSb=GaAs QDs. Faster write/erase times below 1 ns are proposed for improved device structures. 2. QD-Flash: a novel QD-based memory

 Corresponding author. Tel.: +49 30 314 21977; fax: +49 30 314 22569.

E-mail address: [email protected] (A. Marent). Present address: Department of Physics and CeNIDE, Universita¨t DuisburgEssen, Lotharstrasse 1, 47048 Duisburg, Germany. 1

0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.06.056

Within the novel memory concept, the so-called QD-Flash [7], QDs are placed inside a p–n diode structure, nearby or inside the depletion region and act as storage units. The QD-Flash eliminates

ARTICLE IN PRESS A. Marent et al. / Microelectronics Journal 40 (2009) 492–495

493

Fig. 1. Schematic illustration of the storage (a), write (b), and erase (c) process in the proposed QD-based Flash memory based on hole storage.

1 Ma Storage time (s) at 300 K

the drawbacks of the ‘‘fixed height’’ of SiO2 barriers by using barriers whose height can be decreased during the write operation [11]. The charge carrier storage and the write/erase operations work as follows, schematically depicted in Fig. 1 for hole storage: At zero bias, the doping concentration and the location of the QDs in the structure is adjusted such that the QDs are inside the depletion region. This represents the storage situation, Fig. 1(a). The width of the depletion region can be changed by an applied external bias. A forward bias reduces the width and the QDs are outside the depletion region, Fig. 1(b). Hence, in contrast to the Flash memory concept with the fixed SiO2 barrier height, the capture barrier is eliminated and very fast capture into the QD states is possible. To erase the information, a high reverse bias is applied to the diode, Fig. 1(c). The QDs are inside the depletion region with a strong electric field enabling tunneling of the charge carriers through the triangular barrier.

10 a

108

24 h

1

10-8

0.2

0.4

0.6 0.8 1.0 1.2 Localization energy (eV)

1.4

2.1. Storage times in self-organized QDs A first milestone to use QDs as storage units is to demonstrate a storage time in the order of milliseconds, the crucial DRAM refresh time. As the storage time in QDs depends on the localization energy of the charge carriers, material combinations with a large band offset between QD and matrix are promising. We have previously determined storage times and localization energies of holes in a number of QD material systems [10,12–15] using deep level transient spectroscopy (DLTS) [16]. An increase in the hole storage time at room temperature by more than nine orders of magnitude from nanoseconds up to seconds was observed as the hole localization energy increases from 210 meV in InAs=GaAs QDs up to 710 meV in InAs=GaAs QDs with an additional Al0:9 Ga0:1 As barrier. This localization energy leads to a hole storage time of about 1.6 s at room temperature, three orders of magnitude longer than the crucial DRAM refresh time [10]. The experimental results are plotted in Fig. 2 as full circles. The storage time shows an exponential dependence on the localization energy as predicted by the common rate equation of thermally activated emission [16]. It increases by one order of magnitude for an increase in the localization energy of about 50 meV. From the experimental results a hole localization energy can be estimated, which provides a storage time of 24 h and 10 years. These storage times are reached for localization energies of 0.96 and 1:14 eV, respectively. We calculated the hole localization energies for different antimony-based QDs using 8-band k  p theory [10,17] to estimate the hole storage times at room temperature. The results are summarized in Table 1 and plotted in Fig. 2 as open circles. A hole storage time in InSb=GaAs QDs of more than 24 h is predicted. Using Alx Ga1x As instead of GaAs as matrix material, a storage time of more than 10 years can be achieved. Since the valence band offset between GaAs and AlAs is about 550 meV [18] the

Fig. 2. Hole storage time versus the localization energy for different QD systems. The solid line is a fit to the experimental data (full circles). The open circles are predicted storage times.

Table 1 Hole localization energies in different Sb-based QDs calculated by 8-band k  p theory QDs/matrix

Localization energy

Estimated storage time

GaAs0:5 Sb0:5 =GaAs GaSb=GaAs In0:5 Ga0:5 Sb=GaAs InSb=GaAs GaSb=AlAs

350 meV 853 meV 919 meV 996 meV 1:4 eV

0:1 ms 13 min 4h 6 days 4106 years

The storage time at room temperature is estimated according to the fit of the experimental data in Fig. 2.

entire hole localization energy in GaSb=AlAs QDs is about 1:4 eV. This value leads to an average hole storage time of more than one million years at room temperature (see Fig. 2), orders of magnitude longer than needed for a nonvolatile memory. Therefore, based on the experimental results, type-II ðInÞðGaÞSb QDs in a AlðGaÞAs matrix are considered to be a very promising material combination for a future nonvolatile QD memory.

3. Dynamics of QD memory structures To prove the potential of the QD-Flash concept, we have investigated the write and erase process in QD-based memory structures. Two samples were investigated containing type-I InAs=GaAs and type-II GaSb=GaAs QDs in a nþ 2p diode [11]. This allows measuring write and erase times with holes. The charge

ARTICLE IN PRESS A. Marent et al. / Microelectronics Journal 40 (2009) 492–495

Max. hysteresis opening Cmax (a. u.)

494

1.0

0.5

0 10-5

10-3 10-1 Erase pulse width (s)

10

1000

Fig. 4. Maximum hysteresis opening C max for different erase pulse widths and three selected applied reverse biases in a GaSb QD memory structure.

Fig. 3. Maximum hysteresis opening C max for different write pulse widths. The inset shows the capacitance sweep of a nþ 2p diode containing GaSb=GaAs QDs.

state of the QDs were read-out by measuring the capacitance of the nþ 2p diode. A larger capacitance corresponds to unoccupied QDs (‘‘0’’), while a smaller capacitance represents a ‘‘1’’, where the QDs are filled with holes. The maximum hysteresis opening is defined at the storage position as the difference between both capacitance values for a ‘‘0’’ and ‘‘1’’ state. The inset in Fig. 3 shows the switching between the two states by a hysteresis curve of the capacitance for the GaSb QD sample. 3.1. Write times in QD memory structures To study the write time, series of write pulses were applied with decreasing pulse widths down to 300 ps. The measurement cycle started with a 10 s long erase pulse (Point 1 in the inset of Fig. 3). Then, the capacitance of the device structure was measured at the storage position (Point 2). A write pulse was applied to the device (Point 3) and the capacitance was again measured at the storage situation (Point 4). Fig. 3 shows the maximum hysteresis opening C max versus the write pulse width. The limit of the write time is reached when the QDs are not sufficiently charged anymore. The hysteresis opening C max vanishes and we define the limit as a drop in C max to 50 percent. A minimum write time of 6 ns for the InAs QD sample is obtained. For the GaSb QD sample—having a hole localization energy which is more than twice as high—we measured a write time of 14 ns. Three orders of magnitude faster than for present Flash cells. Both write times are almost equal and already in the order of the write time in a DRAM cell. The measured write times are at the moment only limited by the parasitic cut-off frequency of the RC low pass of the devices, which are slightly different. Much faster write times below 1 ns, as well at room temperature, which are independent of the localization energy should be feasible for improved memory structures having higher external cut off frequencies.

barrier. One expect an exponential dependence of the emission rate and, hence, of the erase time on the electric field [12,19]. Therefore, the erase time in the QD-Flash can be adjusted by the doping concentration of the p–n diode and the applied reverse bias. We have investigated the erase operation using the GaSb QD memory structure, the same structure as for the write time measurements before [11]. The measurement cycle is now reversed to the write time investigations. The capacitance is measured after a 2s-write pulse, which completely fills the GaSb QDs with holes. An erase pulse was applied to the device and the maximum hysteresis opening C max was determined afterwards. We applied different erase pulse voltages from 10 up to 20 V to measure the dependence of the emission rate on the electric field. Fig. 4 shows the decrease of C max for three selected erase pulse voltages. The erase time limit is again defined as a drop in C max to 50 percent. We obtain erase times from 16 s down to 1:5 ms by increasing the electric field from 95 up to 206 kV=cm. The hole localization energy of GaSb QDs leads to a storage time at 100 K which is sufficiently long enough for one measurement cycle. At this temperature, the underlaying emission process is phonon-assisted tunneling [20–22]. As a consequence, a strong dependence of the erase time on the temperature is expected. Fig. 5 shows the hole emission rate—which is the reciprocal value of the erase time obtained in Fig. 4—versus the inverse electric field for different temperatures. Pure thermal emission occurs for small electric fields and high temperatures, hence, for an inverse electric field greater than 8 cm=MV and a temperature higher than 100 K an almost constant emission rate is visible in Fig. 5. At high electric fields, the emission rate is independent of the temperature and pure tunneling occurs, clearly indicated by an exponential dependence of the emission rate on the inverse electric field [12]. Using a linear fit to the data, an erase time below 10 ns can be extrapolated for an electric field of more than 500 kV=cm. Band structure engineering of future memory structures may allow to optimize the emission barrier yielding a faster erase time also in combination with longer storage times. 4. Conclusion

3.2. Erase times in QD memory structures According to our QD-Flash concept, the erase process is realized by applying a reverse bias to the diode. The increased electric field at the position of the QDs leads to an increase of the tunneling probability out of the QDs through the triangular

We have presented a memory concept based on self-organized QDs, enabling very fast write times in combination with long storage times. Based on our experimental results we predict a storage time of 106 years in GaSb=AlAs QDs, orders of magnitude longer than needed for a nonvolatile memory. The physical

ARTICLE IN PRESS A. Marent et al. / Microelectronics Journal 40 (2009) 492–495

by the SANDiE Network of Excellence of the European Commission, Contract number NMP4-CT-2004-500101, by the QD-Flash project in the framework of ProFIT of the Investitionsbank Berlin (IBB) and by the DFG, Contract number BI 284/29-1.

Electric field (kV/cm) 500

250

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109 107 Emission rate (1/s)

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References

105 103 101 10-1 10-3 10-5 1

2

3

4 5 6 7 8 Inverse electric field (cm/MV)

9

10

11

Fig. 5. Emission rate in a GaSb QD memory structure as function of the inverse electric field on a semilogarithmic scale for different temperatures. Pure tunneling occurs for high electric fields, indicated by an exponential dependence of the emission rate on the electric field. The black solid line is a linear fit used to estimate an electric field of more than 500 kV/cm to reach an erase time below 10 ns.

limitation of the write time in such a QD-based memory is given by the relaxation time of the charge carriers, known to be in the picosecond range. We have investigated the performance of our QD memory structures in terms of write and erase time. We demonstrated a write time of 14 ns in GaSb=GaAs QDs and 6 ns for InAs=GaAs QDs. These write times are at the moment limited by the parasitic cut-off frequency of the RC low pass of the devices. Faster write times below 1 ns are expected for improved device structures. We measured erase times in GaSb QD memory structures in dependence on the applied reverse bias and determined an erase time of 1:5 ms for an electric field of 206 kV=cm. Erase times below 10 ns in GaSb QDs are expected for an electric field of about 500 kV=cm.

Acknowledgments We acknowledge contributions from many colleagues in different institutions: T. Nowozin, A. Schliwa, D. Feise, and ¨ ncan from Istanbul K. Po¨tschke from TU Berlin. N. Akc- ay and N. O University. A.P. Vasi’ev, E.S. Semenova, A.E. Zhukov, and V.M. Ustinov from Ioffe Institute. The work was partly funded

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