Assembly process automation. Part 2. VLSI design rules

Assembly process automation. Part 2. VLSI design rules

788 World Abstracts on Microelectronics and Reliability Planarization techniques for multilevel metallization. A. N. Multilayer resist processing: ...

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788

World Abstracts on Microelectronics and Reliability

Planarization techniques for multilevel metallization. A. N.

Multilayer resist processing: economic considerations. JOHN

SAXENAand D. PRAMANIK.Solid St. Technol., 95 (October 1986). Multilevel metaUization is becoming increasingly important in VLSI in order to increase circuit density and performance. Planarization in multilevel metallization is utilized to smooth out topographic undulations caused by conductors, dielectrics, contacts and vias. This helps to enhance yield. Various methods for planarizing metals and dielectrics are discussed.

LEE. Solid St. Technol., 143 (June 1986). Process and cost details of six multilayer resist processing schemes are compared and analyzed. An economic model keyed to a production capacity of 40 million good dies per year is then used to choose the process with the lowest yielded die cost.

Molecular beam epitaxy of semiconductor, dielectric and metal films. S. I. STENIN. Vacuum 36(7-9), 419 (1986). The principles of molecular beam epitaxy (MBE), MBE equipment and analytical devices for MBE process monitoring in situ are presented. The main problems of semiconductor film MBE are formulated and their solutions are discussed. The possible uses of MBE for the preparation of metal films on semiconductors with perfect interfaces having the desired properties are analysed. Two techniques for the fabrication of insulator epitaxial films on semiconductor crystals are described. In conclusion the applications and trends in the development of MBE are discussed.

Ionizing radiation in microelectronics processing. CHARLESM. DOZlER. Solid St. Technol., 105 (October 1986). Ionizing radiations generated during the lithography and dry processing stages of microelectronic device fabrication can produce damage in the underlying materials. Results of recent studies on the nature of the radiation defects produced during irradiation in MOS structures are reviewed. A model developed for generation of interface states at the oxidesemiconductor boundary suggests that the processes used to anneal radiation defects may in fact produce latent sites which can be reactivated readily by either subsequent radiation or operational hazards such as hot electrons. A tool for aggregate production planning. BRUCE W1EDER. Semiconductor int., 204 (May 1986). A descriptive model offers the capability for linking operational planning to strategic planning in semiconductor manufacturing.

Assembly process automation. Part 2. VLSI design rules. JEFF BRADEN. Semiconductor int., 178 (May 1986). The success of an assembly automation program depends on repeatable and controllable assembly processes.

Lithography impact on printed wiring boards, W. S. FUJITSUBO. Solid St. Technol., 161 (June 1986). As both the silicon and GaAs technologies drive device speeds into the GHz frequency range and rise times to fractions of nanoseconds, the interconnections role of printed wiring circuitry assume a new, very critical posture. Printed wiring boards must now be designed to channel electro-magnetic waves in the form of transmission lines rather than just voltages and current in conductors. The space between conductors becomes signal paths for electric and magnetic waves to propagate. Control of the physical dimensions of the conductors and the spacing between conductors determines the impedance and cross-talk characteristics. The tolerances in these dimensions will determine ultimately the very high speed systems performance. These dimensional tolerances will place additional stringent requirements on the photolithographic equipment, which has been used traditionally in the printed wiring industries. This article discusses the impact of very high density interconnection, the effect of the dielectric material on propagation of signal speeds, the requirements for controlled characteristic impedances, and the concern for isolation of signals or cross-talk on future printed wire board design and fabrication processes.

Design, manufacture, and assembly of high pin count plastic pin grid array packages. MARTIN F. BLACKSHAW and FRANCISJ. DANCE.Solid St. Technol., 141 (August 1986). The proliferation of VLSI technology in gate array and standard cell custom chip configurations, as well as 32 bit microprocessors, is necessitating the developments of new, high performance, high pin count packaging techniques. The use of pin grid arrays as an immediate packaging solution, is already widely employed. The design, manufacture, and assembly of plastic pin grid array packages are proposed to resolve some of the concerns which arise when the traditional alumina ceramic with tungsten, molybdenum or gold metallization is employed. This technology, based upon advanced printed circuit board processing techniques, offers improved electrical and thermal performance, lower cost, and reduced lead time from design to production.

Simultaneous placement and routing in integrated circuits. LADISLAVSZANTOand ZDENEKBURJAN.TESLA Electron. 1, 23 (1985). The commonly accepted approach to chip layout design based on predefined leaf blocks goes through the following three stages: placement, signal nets routing and power nets laying. The crucial deficiency of this approach is the lack of exact information bits, as the results of the three consecutive stages are interdependent. This paper presents the Simultaneous Placement and Routing Method (SIPRM) which deals with exactly defined data at every stage of design. The corresponding data structure is simple and data managing is straightforward. The method is implemented in the SIPR program whose turning-points are disclosed in the paper.

Autodoping and particulate contaminations during prediffusion chemical cleaning of silicon wafers. [QBAL K. BANSAL. Solid St. Technol., 75 (July 1986). Autodoping impurities and particulate contamination on silicon wafers during pre-diffusion chemical cleaning were evaluated. The C-V characteristics analysis using a MOS capacitor was employed to determine the profile of autodoping impurities. Particulate contaminations were measured using a laser beam scanning system. Comparative particle count data, with and without a point-of-use ultrafiltration membrane system for the deionized water are also discussed.

Silicon compilation and design for test. ANN H. DOERR and DENNlS G. SA,O. Solid St. Technol., 117 (August 1986). Design for test using silicon compilation is discussed. This is preceded by an overview of silicon compilation which compares silicon compilation to other Application Specific IC (ASIC) design methodologies.

Dry etch chemical safety. JEANOHLSON.Solid St. Technol., 69 (July 1986). Potential hazards of dry etch equipment are investigated. Possible exposures in operating and maintaining the equipment are examined. Gas composition was analyzed at the output of the etch chamber and at the system exhaust, thus providing an understanding of potential emission hazards. To evaluate maintenance exposures, etch chamber residue and vacuum pump oils were analyzed. A variety of equipment/process combinations was investigated. Test results and precautionary measures are presented.

Hazardous production gases. Part 2. Toxicity and hazards. RlCHARD A. BOLMENJR. Semiconductor int., 231 (May 1986). Understanding the hazards of process gases is the responsibility of the engineer installing the fabrication system.

Wet-chemical etching of SiO2 and PSG films, and an etchinginduced defect in glass-passivated integrated circuits. WERNER