Materials Science and Engineering C 26 (2006) 867 – 870 www.elsevier.com/locate/msec
Electrical characterization of InAs/GaAs quantum dot structures E. Gombia a,*, R. Mosca a, S. Franchi a, P. Frigeri a, C. Ghezzi b b
a IMEM-CNR Institute, Parco Area delle Scienze, 43010 Fontanini, Parma, Italy Istituto Nazionale per la Fisica della Materia, Department of Physics, University of Parma, Parco Area delle Scienze, 43100 Parma, Italy
Available online 20 October 2005
Abstract The electrical properties of InAs quantum dots (QD) in InAs/GaAs structures have been investigated by space charge spectroscopy techniques, current – voltage and capacitance – voltage measurements. Au/GaAs/InAs(QD)/GaAs Schottky barriers as well as ohmic/GaAs/ InAs(QD)/GaAs/ohmic structures have been prepared in order to analyze the apparent free carrier concentration profiles across the QD plane, the electronic levels around the QD and the electrical properties of the GaAs/InAs(QD)/GaAs heterojunction. Accumulation and/or depletion of free carriers at the QD plane have been observed by Capacitance – Voltage (C – V) measurements depending on the structure parameters and growth procedures. Similarly, quantum dot levels which exhibit distributions in energy have been detected by Deep Level Transient Spectroscopy (DLTS) and Admittance Spectroscopy (AS) measurements only on particular structures. Finally, the rectification properties of the InAs/GaAs heterojunction have been investigated and the influence of the related capacitance on the measured capacitance has been evidenced. D 2005 Elsevier B.V. All rights reserved. Keywords: Self-assembled quantum dots; Capacitance – voltage method; Current – voltage measurements
1. Introduction Quantum dots (QD) are attracting a growing attention from the viewpoint of fundamental physics as well as for technological applications in novel optoelectronic devices such as laser and optical memory structures. The characteristics of these devices strongly depend on the electronic levels induced by QDs. Many authors have investigated by photoluminescence (PL) techniques the optical properties of systems containing QDs providing information on the transition energies between electron and hole levels in QDs . On the other hand, electrical methods such as space charge spectroscopy techniques are expected to give the position of quantum levels relative to the band structure of the host matrix [2 –7], that is information complementary to that achieved by PL. However electrical measurements give results whose interpretation cannot be straightforward due to (i) the peculiar properties of the quantum levels, (ii) the presence of deep levels possibly connected to the growth of the QDs, (iii) the multi-layer structure the QDs are embedded in, (iv) the * Corresponding author. E-mail address: [email protected]
(E. Gombia). 0928-4931/$ - see front matter D 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.msec.2005.09.018
geometry of the devices. In this work different GaAs/ InAs(QDs)/GaAs structures are investigated by Capacitance – Voltage (C – V), Admittance Spectroscopy (AS) and Deep Level Transient Spectroscopy (DLTS) techniques in order to obtain information about the quantum levels of the dots as well as the electronic levels induced by point or extended defects. Furthermore particular attention has been devoted to the study of the current –voltage (I – V) characteristics through the QDs and to the evaluation of a possible depletion layer at the QD plane. 2. Experimental The samples investigated were grown in a Varian Gen II Modular MBE system on n+ GaAs substrates. They consist of a 1 Am thick n-GaAs buffer layer with electron concentration N = 8 –10 1015 cm 3, an InAs layer with a coverage ranging from 1 to 3 monolayers (ML), and a topmost n-GaAs layer, with N = 6 – 12 1015 cm 3 and thickness ranging from 0.6 to 1.0 Am. When the coverage of the mismatched InAs layer on GaAs is above the critical value of 1.6 ML, the growth of a continuous two-dimensional InAs layer turns to the formation of self-assembled three-dimensional QDs according to the
E. Gombia et al. / Materials Science and Engineering C 26 (2006) 867 – 870
Stransky-Krastanov growth mode. InAs coverages of 1 and 3 ML results in a pseudomorphic layer (PSL) and a 1.6 ML wetting layer with InAs QD, respectively. After the growth of the buffer layer at 580 -C the substrate temperature was reduced to 460 -C for the deposition of InAs by atomic layer MBE (ALMBE). The upper GaAs layer was grown by ALMBE at 400 -C and/or by MBE at 580 -C. Finally reference samples without any InAs layer but grown under the same conditions of the corresponding QD or PSL samples have been prepared to investigate the structure properties not affected by the InAs insertion. After the formation of the AuGeNi ohmic contacts on the backside of the n+ GaAs substrate, circular Au Schottky contacts, 400 Am in diameter, were prepared by photolithography on the cap layers. Ohmic/GaAs/InAs/GaAs/ohmic mesa structures, 500 Am in diameter and 2.5 Am deep, were also obtained by etching in H2SO4 –H2O2 – H2O (5:1:1) solution in order to investigate the transport properties through the GaAs/InAs/GaAs structures and to assess the influence of a possible depletion layer at the QD plane on the measured capacitance of the Au/GaAs/InAs/ GaAs Schottky barrier. Capacitance – voltage (C – V) and Admittance (AS) measurements were performed by a 4192A HP impedance analyzer at frequency of 1 MHz using a test signal amplitude of 15 mV. Current –voltage (I – V) characteristics were obtained by a Keithley 236 source-measure unit while DLTS measurements were carried out by a high sensitivity lock-in type spectrometer in the 30 –350 K temperature range. 3. Results and discussion All the structures with quantum dots were first investigated by photoluminescence measurements carried out at 10 K with low excitation power. All the spectra show characteristic peaks due to transitions between the ground state of electrons and holes confined in the QD. Fig. 1 reports the C – V profiles obtained at different temperatures on a QD sample with an InAs coverage of 3.0 2 1016 145 K 35 K
1.6 1016 1.2 1016
depth (µm) Fig. 1. Capacitance – voltage profiles obtained at different temperatures on an Au/GaAs/InAs(QD)/GaAs structure with a GaAs cap grown partially by ALMBE (0.4 Am) and by MBE (0.6 Am). Test signal frequency = 1 MHz.
60 +0.4 V +0.2 V 0 V -0.2 V -0.4 V -0.8 V -1.0 V
30 20 10 0 60
Temperature (K) Fig. 2. Conductance measurements as a function of temperature obtained for different applied biases on the Au/GaAs/InAs(QD)/GaAs structure with a GaAs cap grown partially by ALMBE (0.4 Am) and by MBE (0.6 Am). Before the Schottky contact formation a thickness of 0.35 Am of GaAs cap has been removed by etching.
ML and a GaAs cap grown by ALMBE at 400 -C for 0.4 Am and by MBE at 580 -C for the subsequent 0.6 Am. A significant carrier depletion and a peak located at a depth corresponding to the position of the InAs plane can be clearly observed. The peak, which is detected at temperatures below 200 K only on samples with QD, shifts towards larger distances from the metal – semiconductor interface as the temperature decreases. Taking into account that the PSL sample shows a depletion similar to the QD sample but without any accumulation peak, it has been suggested  that the carrier reduction around the InAs plane is due to a high density of acceptor-like levels and that the carrier accumulation is related to electrons in the QD and/or the wetting layer. Since the peak appears only at T < 200 K, at higher temperatures the QD and/or the wetting layer related levels are likely located above the Fermi level. The shift of the accumulation peak to larger depths when the temperature is decreased has been ascribed to the reduction of the emission rate of the above levels . Admittance Spectroscopy measurements, carried out on the same structure from which a thickness of 0.35 Am of GaAs cap has been removed by etching, show a low temperature conductance peak (see Fig. 2), whose position moves towards higher temperatures by increasing the reverse bias Vr. This peak, which is not present in the PSL sample and is detected only when the region near the QD is investigated, can be ascribed to a distribution of levels located around the QD plane. The activation energy of the highest conductance peak, corresponding to the center of the level distribution, has been estimated to be about 60 meV from the GaAs conduction band. This value is in fair agreement with the activation energy of a low temperature DLTS peak , detected only on the QD sample and only when the QDs are inside the depletion layer of the Schottky barrier. This DLTS peak exhibits an emission rate independent on the temperature in the 40 – 60 K range indicating an emission mechanism dominated by tunneling that has been already observed for quantum dot levels in InAs/ GaAs structures . The above results are consistent with the
E. Gombia et al. / Materials Science and Engineering C 26 (2006) 867 – 870
10-2 10-3 after annealing
hypothesis that the low temperature DLTS and AS peaks could be attributed to a distribution of quantum levels induced by the dots. However it should be pointed out that the results of both C – V and space charge spectroscopy techniques on QD samples have been observed to strongly depend on the growth parameters of the GaAs and InAs layers as well as on the structure design. Indeed the experimental results reported for GaAs/InAs(QD)/GaAs structures grown in different laboratories [6– 8] show marked differences probably due to the different techniques used to grow the QDs and the difficulties in reproducing the same growth conditions. As a consequence carrier accumulation peaks and quantum levels associated to QD in some cases are not clearly detectable by the above space charge spectroscopy techniques. As an example Fig. 3 shows the C – V profiles of a QD sample which differs from that of Fig. 1 for the fact that the GaAs cap has been grown completely by MBE at 580 -C. The profiles show a carrier depletion near the QD plane but no accumulation peak in the 30– 300 K temperature range. Furthermore in these samples no deep level has been observed in the region near the InAs layer by DLTS and AS measurements. A possible explanation for the absence of accumulation peaks and DLTS signals even at low temperatures may be attributed to the fact that, due to acceptor states, the Fermi level is below the QD related levels at zero bias; indeed in these conditions it is not possible to change the occupancy state of the levels by changing the reverse bias applied to the Schottky barrier and consequently carrier accumulation or DLTS peaks are not detected. However the above interpretation should be reconsidered taking into account that the presence of the QD plane affects the measured capacitance and then the CV profiles. In fact the analysis of capacitance measurements on these samples is not straightforward as it is also evidenced by I – V and C –V measurements obtained by using AuGeNi as the metal top contact on the structures discussed in Fig. 3. In order to study the properties of the GaAs/InAs/GaAs heterojunction measurements have been performed before and after annealing of the top contact at 350 -C on samples with and without mesa. Before annealing, when the top contact is a Schottky barrier, the mesa structure shows a
10-5 10-6 before annealing
10-7 10-8 10-9 10-10 0
Voltage (V) Fig. 4. Current – voltage characteristics of an AuGeNi/GaAs/InAs(QD)/GaAs/ AuGeNi mesa structure (500 Am in diameter) before and after annealing of the AuGeNi top contact at 350 -C. Symbols indicate that the voltage applied to the surface contact is negative for empty and full circles and positive for empty and full squares.
very low reverse current and a strongly non-ideal forward characteristic (Fig. 4). After annealing, when the top AuGeNi contact is an ohmic contact, a clear rectifying characteristic is observed, with a reverse current very close to the forward current before annealing. This behaviour can be explained by considering the samples before annealing as made by two diodes connected back to back (namely the AuGeNi/GaAs Schottky barrier and the barrier at the QD plane) while after annealing the rectifying characteristics are determined only by the barrier at the QD plane. Indeed, the diodes without mesa, where the QD area is about 40 mm2, show good rectifying 10-2 10-3 after annealing
10-5 30 K 80 K
10-8 10-9 10-10 15
Voltage (V) 0.4
depth (µm) Fig. 3. Capacitance – voltage profiles taken at different temperatures on an Au/ GaAs/InAs(QD)/GaAs structure with a GaAs cap grown by MBE.
Fig. 5. Current – voltage characteristics of an AuGeNi/GaAs/InAs(QD)/GaAs/ AuGeNi structure without mesa (sample area = 40 mm2) before and after annealing of the AuGeNi top contact at 350 -C. Symbols indicate that the voltage applied to the surface contact is negative for empty and full circles and positive for empty and full squares.
E. Gombia et al. / Materials Science and Engineering C 26 (2006) 867 – 870
QD area. This is confirmed by the observation that the capacitance measured before annealing in samples with mesa is comparable with that of samples without mesa (Fig. 6).
with mesa, after annealing at 350 °C without mesa, before annealing with mesa, before annealing
50 40 30 20 10 0
Voltage (V) Fig. 6. Capacitance – voltage characteristics obtained on an AuGeNi/GaAs/ InAs(QD)/GaAs/AuGeNi structure (i) without mesa and no annealing, (ii) with mesa and no annealing and (iii) without mesa and annealing at 350 -C, respectively.
characteristics before annealing due to the top Schottky contact, while a quasi-ohmic behaviour is observed after annealing (see Fig. 5) as a consequence of the large area of the InAs/GaAs heterojunction which strongly affects the reverse current. The presence of a barrier at the QD region results in a capacitance that is evidenced by C – V measurements. Indeed C –V curves shown in Fig. 6 can be explained considering that (i) in the sample with mesa the capacitance after annealing is determined by the QD region (C QD) because no surface Schottky barrier is present, (ii) in the structure without mesa before annealing the capacitance associated to the QD region is in series with the metal/GaAs capacitance (C D); however, since the area of the InAs/GaAs heterojunction is much larger than that of the metal/GaAs contact, the capacitance measured at low biases, when the depletion regions do not interact, is C D, (iii) in the sample with mesa before annealing the area of the QD region is comparable with that of the Schottky barrier so that at low biases the capacitance is expected to be the series of C QD and C D. As it can be noted from Fig. 6 the capacitances measured at zero bias are C QD = 79 pF and C D = 55 pF. The series of these two capacitances gives a value of 32 pF, in good agreement with the capacitance measured on the sample with mesa before annealing where the two noninteracting depletion layers are present. Furthermore, at high reverse voltages, when the electric field of the Schottky barrier is pushed beyond the QD plane, the capacitance is determined by depletion region of the Schottky contact and is expected to be weakly affected by the
Two typical GaAs/InAs(QD)/GaAs structures with different GaAs cap layers have been investigated by space charge spectroscopy techniques. In the first structure a clear accumulation peak is observed in the C – V profile. Moreover a distribution of levels, centered at about 60 meV from the bottom of the GaAs conduction band, has been detected. This level distribution has been ascribed to QD-related states. In the second structure no accumulation peak in the C – V profile and no traps related to QD have been observed. This suggests that the multi-layer structure the QDs are embedded in strongly influences the detection of electronic levels induced by the dot. It has been demonstrated that the GaAs/InAs(QD)/GaAs junction shows rectifying properties which depend on the quantum dot characteristics and that the related capacitance strongly influences the measured capacitance of structures containing the above junction. Acknowledgements This work has been partially supported by the FIRB Project ‘‘Nanotecnologie e Nanodispositivi per la Societa` dell’Informazione’’ and by ‘‘SANDiE’’ network of excellence of EU, Contract No. NMP-CT-2004-500101. References  D. Bimberg, M. Grundman, N.N. Ledentsov, Quantum Dots Heterostructures, Wiley, New York, 1999.  P.N. Brunkov, S.G. Konnokov, V.M. Ustinov, A.E. Zhukov, A.Yu. Egorov, M.V. Maksimov, N.N. Ledensov, P.S. Kop’ev, Semiconductors 30 (1996) 492.  S.K. Zhang, H.J. Zhu, F. Lu, X. Wang, Phys. Rev. Lett. 80 (1998) 3340.  R. Magno, Brian R. Bennet, E.R. Glaser, J. Appl. Phys. 88 (2000) 5843.  S. Anand, N. Carlsson, M.E. Pistol, L. Samuelson, W. Seifert, J. Appl. Phys. 84 (1988) 3747.  S. Ghosh, B. Kochman, J. Sing, P. Bhattacharya, Appl. Phys, Lett. 76 (2000) 2571.  C. Walther, J. Bollmann, H. Kissel, H. Kirmse, W. Neumann, W.T. Masselink, Phys., B Condens. Matter 273 – 274 (1999) 971.  E. Gombia, R. Mosca, P. Frigeri, S. Franchi, S. Amighetti, C. Ghezzi, Mater. Sci. Eng., B, Solid-State Mater. Adv. Technol. 91 – 91 (2002) 393.  C.M.A. Kapteyn, F. Heinrichsdorff, O. Stier, R. Heitz, M. Grundmann, N.D. Zakharov, D. Bimberg, Phys. Rev., B 60 (1999) 14265.