Enhanced gate induced drain leakage current in HfO2 MOSFETs

Enhanced gate induced drain leakage current in HfO2 MOSFETs

Microelectronic Engineering 86 (2009) 2157–2160 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier...

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Microelectronic Engineering 86 (2009) 2157–2160

Contents lists available at ScienceDirect

Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee

Enhanced gate induced drain leakage current in HfO2 MOSFETs Moshe Gurfinkel a,*, John S. Suehle b, Yoram Shapira a a b

School of EE, Tel Aviv University, Tel Aviv 66978, Israel Semiconductor Electronics Division, NIST, Gaithersburg, MD 20899, USA

a r t i c l e

i n f o

Article history: Received 4 November 2008 Received in revised form 11 February 2009 Accepted 25 February 2009 Available online 6 March 2009 Keywords: Gate Induced Drain Leakage (GIDL) High-j Dielectrics Substrate current

a b s t r a c t The substrate current of high-j dielectric MOSFETs has been studied using dc sweep and transient (down to 100 ls per I–V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-toband tunneling assisted by traps located at the HfO2/SiO2 interface and transition layer, and not the result of oxide charging. Ó 2009 Elsevier B.V. All rights reserved.

1. Introduction

2. Experimental setup

The downscaling of the MOSFETs gate dielectric thickness has reached its physical limit. To provide sufficient gate control of the continuously shrinking transistor channel while keeping low gate leakage, high dielectric materials are introduced into the CMOS process technology [1]. One of the key issues in high-j gate stacks is the high density of traps in the bulk of the high-j layer, at the high-j/SiO2 interface and in the high-j/SiO2 transition layer. These traps degrade the device performance and reliability [2,3]. In addition, transient charge trapping complicates electrical characterization [4]. The substrate current in MOSFETs is a result of electron-hole pair generation due to impact ionization of high energy carriers. As the gate voltage increases, the number of carriers in the channel increases. At the same time, the lateral electric field, and consequently the impact ionization probability, decreases. Hence, the substrate current as a function of the gate voltage has a unique bell shape [5]. In this work, we show that the substrate current of high-j MOSFETs exhibits two additional trap-related current components, as compared with the traditional bell-shaped impact ionization current. Based on the experimental data, we demonstrate that at low gate biases trap-assisted gate induced drain leakage (GIDL) dominates the substrate current, while at high gate biases, trap-assisted-tunneling of valence band electrons from the bulk to the gate dominates.

The devices used in this work are fully processed n-channel MOSFETs with HfO2/SiO2 stacked gate dielectrics. High-j gate dielectric transistors were fabricated on 200 mm p/p+ epitaxial Si h1 0 0i wafers using a standard CMOS process with a 1000 °C, 10 s dopant activation step. The gate stacks were formed by atomic layer deposition of a 3 nm HfO2 dielectric on 1 nm thermal oxide interfacial layer created by a controlled etch-back of a 1.9 nm thick thermal oxide. The high-j film deposition was followed by a 700 °C anneal in an NH3 ambient after which a gate electrode was formed by chemical vapor deposition (CVD) of TiN with poly-Si cap [6]. Optimized lightly doped drain (LDD) and a halo implant were used to insure the proper overlap of the LDD with the gate. We used 2 nm SiO2 (ISSG)/poly gate devices as control devices. All four currents of the device (i.e., source, drain, gate and bulk currents) were measured simultaneously using a semiconductor parameter analyzer. Using the experimental setup from Gilibert et al. [7], the effects of the vertical and lateral electric fields under the gate may be separated. The measurement setup is illustrated in Fig. 1. Thus, we could separately measure the pure GIDL component of the drain current. Initially, the junction leakage (IL) as a function of VDB is separately measured by biasing the bulk and keeping the other terminals grounded (configuration A). The total junction current (IL + IGIDL) is further measured as a function of VGS by sweeping the gate voltage while keeping VDB constant (configuration B). Finally, the GIDL current is extracted by subtracting the two measurements. This separation is based on the assumption that the junction leakage depends only on VDB while the GIDL depends only on VDG. This assumption is only an approximation. However, if the gate-induced depleted area in the drain is

* Corresponding author. Tel.: +972 3 6408015. E-mail address: [email protected] (M. Gurfinkel). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.02.029

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Fig. 2. Transient substrate current measurement setup.

Fig. 1. GIDL Measurement setup: configuration A to get IL as a function of VDB, configuration B to get IL and GIDL as a function VDG. The GIDL current is extracted by subtracting the two measurements.

negligible compared to the junction perimeter, this is a good approximation. To eliminate all other current components, such as channel current, gate tunneling current, sub-threshold diffusion current, and bulk punch-through current, we used a long channel transistor (minimizing the punch-through current) with a physically thick gate oxide (minimizing the gate tunneling). In addition, the drain and source were short-circuited to minimize the sub-threshold leakage and channel current. Ultra-fast measurements of the substrate current were performed using a low-noise and high-speed operational amplifier. The basic setup was taken from Shen et al. [8], who described an ultra-fast drain current measurement setup. However, the transimpedance was adjusted to suit the smaller current values. Fig. 2 shows the schematic of the ultra-fast substrate current measurement. The parasitic capacitance and resistance of the substrate limit the speed of the measurement. Thus, we had to dice an individual die out of the wafer to reach a measurement time of 100 ls. A faster measurement time is expected for smaller substrate sizes. 3. Results and discussion 3.1. Substrate current Fig. 3 shows the substrate current as a function of VGS (with VDS as a parameter) for MOSFETs with high-j gate stack (a) and with SiO2 gate stack (b). The substrate current curves exhibit additional current components compared with the traditional bell-shaped impact ionization curve. At the lower VGS regime (VGS 6 0.3 V), an exponentially decreasing component with a well-defined depen-

Fig. 3. Substrate current as a function of VGS for several drain biases of high-j (a) and SiO2 (b) MOSFETs.

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dence on VDS dominates the high-j device substrate current (Fig. 3a) while totally missing in the SiO2 device (Fig. 3b). At the high VGS regime (VGS P 1.5 V), an exponentially increasing component independent of VDS dominates both the high-j and the SiO2 characteristics. In the next sections we will show that the two additional components are the result of trap-assisted GIDL at the lower VGS regime and band-to-band tunneling of valence band electrons at the high VGS regime. 3.2. Low VGS regime Drain current measurements, that are not shown here, indicate that at low VGS values, almost all of the substrate current flows between the substrate and the drain terminals. This result suggests that this current component may be attributed to GIDL. To validate this assumption, we measured the GIDL current using a special setup [7] (see Fig. 2). Fig. 4 shows the substrate current (open symbols), together with the GIDL current (solid curves), measured as a function of VGS with VDS as a parameter of a n-channel MOSFET with a high-j gate stack. If the GIDL component is subtracted from the total substrate current, the curves become similar to the well known bell-shaped impact ionization current [5] of SiO2-based devices. This result confirms that the exponentially decreasing substrate current component at the lower VGS regime originates from GIDL hole current. In the high VDS and low VGS bias regions, the drain-to-gate bias is sufficiently high to deplete and even invert the n+ drain region under the gate. This causes enhanced electric field and band bending, resulting in a dramatic increase of high field effects, such as bandto-band (BTB) tunneling. The electrons tunnel to the drain and contribute to the drain current. The generated holes are swept to the substrate and contribute to the substrate current. The higher GIDL observed in the high-j devices is attributed to the high density of traps in the bulk of the HfO2, at the HfO2/SiO2 interface and in the transition layer. The traps can enhance the GIDL current via two mechanisms. One possible mechanism is trap-assisted-tunneling via traps located at the HfO2/SiO2 interface and in the transition layer. Another possible mechanism is band bending induced by trapped electrons. The negative charge induced by the trapped electrons in the HfO2 bulk bends the bands upward, enhances the electric field and decreases the tunneling distance [9]. Fig. 5 illustrates the two trap-enhanced physical mechanisms. To test which of the possible mechanisms is operative in generating the enhanced GIDL current, we conducted a special high-

speed measurement of the substrate current. By measuring the substrate current faster than the charging time of the traps in the bulk of the HfO2, we were able to eliminate the transient charging phenomenon. Trap-assisted-tunneling is not affected because these traps are located much closer to the semiconductor and respond much faster than our measurement time. Fig. 6 shows the substrate current as a function of VGS at VDS = 2.5 V for three different measurement times (squares – 100 ls, circles – 200 ms, triangles – dc sweep) of n-MOSFETs with high-j gate stack and with SiO2 gate stack (inset). The I–V curve is measured by sweeping VG

Fig. 4. Substrate current and GIDL component as a function of VGS for several drain biases of a high-j MOSFET.

Fig. 6. Suggested trap-assisted tunneling mechanism. The electrons tunnel to the drain and contribute to the GIDL current. The holes are swept to the substrate and contribute to IB.

Fig. 5. Substrate current as a function of VGS from high-j dielectric and SiO2 dielectric (inset) MOSFETs at VDS = 2.5 V measured using the fast measurement setup at three different measurement times.

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an additional mechanism becomes dominant. Fig. 7 shows the conduction and valence bands, computed with a dual gate dielectric band diagram representation program [11] for two different values of the gate voltage (VGS = 0.5 V and VGS = 1.5 V). For the case of VGS = 1.5 V, tunneling of electrons from the valence band in the bulk to the conduction band of the gate can take place (see Fig. 7b). The holes that are left behind are swept to the substrate terminal and contribute to the substrate current. This contribution to the current increases rapidly since the number of states available for inter-band tunneling increases super-linearly with the gate voltage. Although the valence band electron tunneling current is seen in both the high-j and SiO2 devices, it is expected to be orders of magnitude lower in the high-j device because its oxide physical thickness is doubled. In practice, the tunneling current of both devices is similar. This implies that the enhanced tunneling current is attributed to the high density of traps in the HfO2 and the transition layers, which makes the trap-assisted-tunneling mechanism dominant. Crupi et al. [12] reported a similar increase in the high gate voltages substrate current induced by trap-assisted tunneling of valence band electrons to the gate conduction band in conventional SiO2 MOSFETs after soft breakdown of the gate oxide. In addition, the lower band gap of the HfO2 increases the tunneling probability. 4. Conclusions

Fig. 7. Conduction and valence band profiles, computed with a dual gate dielectric band diagram representation program [11] for different values of the gate voltage: (a) VG = 0.5 V and (b) VG = 1.5 V. For VG = 1.5 V and above, tunneling of electrons from the valence band in the Si bulk to the conduction band of the metal gate can take place. The holes that are left behind are swept to the substrate terminal.

in the positive direction and then back in the opposite direction. A shift in the characteristic represents trapped charge in the dielectric. As expected, there is no transient charging of the oxide in the SiO2 device and the characteristics do not exhibit any dependence on the measurement time. For the high-j device, the GIDL components are identical. However, the bell-shaped impact ionization component exhibit hysteretic behavior at the slower measurement time. This shift in substrate current characteristic is attributed to the VTH shift due to trapped charge in the high-j dielectric [10]. The de-trapping time depends exponentially on the distance from the channel and may reach several milliseconds for traps in the high-j oxide bulk. During the 100 ls measurement, there is not enough time for all the charge to de-trap. Consequently, VTH increases and the impact ionization current shifts to the right. According to the trapped-charge-induced GIDL model (Fig. 5a), the GIDL current should increase as the trapped charge increases, similarly to the device threshold voltage. However, the GIDL component shows independence on the measurement time, which rules out charging of the bulk oxide as the cause of this phenomenon. 3.3. High VGS regime The substrate current vs. VGS curves in Fig. 3 indicate that when VGS is increased above 1.5 V, IB undergoes a steep increase because

The advent of high-j dielectric gate stacks enhances trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization holes current. At low gate biases trap-assisted GIDL dominates the substrate current, while at high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. We demonstrated that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO2/SiO2 interface and transition layer, and not the result of oxide charging. These two current components strongly depend on the density of traps in the high-j layer, high-j/SiO2 interface and transition layer. Therefore, the amplitude of these currents may be used as a figure of merit for the quality of high-j gate stacks. Acknowledgements We would like to thank the International SEMATECH for supplying the samples for this work. This work was funded by the NIST Office of Microelectronics Programs. References [1] G. Groeseneken, L. Pantisano, L.-Å. Ragnarsson, R. Degraeve, M. Houssa, T. Kauerauf, P. Roussel, S. De Gendt, M. Heyns, in: Proceedings of Physical and Failure Analysis of Integrated Circuits (IPFA), 2004, pp. 147–155. [2] W.J. Zhu, J.P. Han, T.P. Ma, IEEE Trans. Electron Dev. 51 (2004) 98–105. [3] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, G. Ghibaudo, IEEE Trans. Dev. Mater. Rel. 5 (2005) 5–19. [4] B.H. Lee, R. Choi, J.H. Sim, S.A. Krishnan, J.J. Peterson, G.A. Brown, G. Bersuker, IEEE Trans. Dev. Mater. Rel. 5 (2005) 20–25. [5] N.D. Arora, M. Sharma, IEEE Trans. Electron Dev. 38 (1991) 1392–1398. [6] J. Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman, P. Majhi, et al., Mater. Res. Soc. (MRS) Symp. Proc. (2004) 341–346. [7] F. Gilibert, D. Rideau, A. Dray, F. Agut, M. Minondo, A. Juge, et al., IEICE Trans. Electron. (2005) 829–836. [8] C. Shen, M.F. Li, X.P. Wang, Y.C. Yeo, D.L. Kwong, IEEE Electron Dev. Lett. 27 (2006) 55–57. [9] J.C. Liao, Y.K. Fang, Y.T. Hou, W.H. Tseng, P.F. Hsu, K.C. Lin, K.T. Huang, T.L. Lee, M.S. Liang, IEEE Elec. Dev. Lett. 29 (2008) 509–511. [10] D. Heh, C.D. Young, G. Bersuker, IEEE Elec. Dev. Lett. 29 (2008) 180–182. [11] R.G. Southwick III, W.B. Knowlton, IEEE Trans. Dev. Mater. Rel. 6 (2006) 136– 145. [12] F. Crupi, G. Iannaccone, I. Crupi, R. Degraeve, G. Groeseneken, H.E. Maes, IEEE Trans. Electron Dev. 48 (2001) 1109–1113.