current control using feedback linearization of three-level four-leg voltage source shunt active power filter

current control using feedback linearization of three-level four-leg voltage source shunt active power filter

Electrical Power and Energy Systems 61 (2014) 629–646 Contents lists available at ScienceDirect Electrical Power and Energy Systems journal homepage...

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Electrical Power and Energy Systems 61 (2014) 629–646

Contents lists available at ScienceDirect

Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes

Hybrid direct power/current control using feedback linearization of three-level four-leg voltage source shunt active power filter M. Bouzidi a,b,⇑, A. Benaissa b, S. Barkat c a

Département de l’Electronique et des Communications, Faculté des Nouvelles Technologies d’Information et Communication, Université Kasdi Merbah, Ouargla 30000, Algeria Département d’Electrotechnique, Faculté des Sciences de l’Ingénieur, Université Djillali Liabes de Sidi Bel Abbes, Sidi Bel Abbes 22000, Algeria c Département d’Electrotechnique, Faculté de Technologies, Université de M’sila, M’sila 28000, Algeria b

a r t i c l e

i n f o

Article history: Received 3 January 2013 Received in revised form 27 March 2014 Accepted 28 March 2014

Keywords: Three-level four-leg shunt active filter Hybrid direct power/current control Feedback linearization Three dimensional space vector modulation

a b s t r a c t This paper proposes a hybrid direct power/current control-three dimensional space vector modulation combined with feedback linearization control for three-phase three-level four-leg shunt active power filter (SAPF). The four-leg SAPF ensures full compensation of harmonic phase currents, harmonic neutral current, reactive power and unbalanced nonlinear load currents. It also regulates its self-sustaining DC bus voltage. The voltage-balancing control of two split DC capacitors of the three-level four-leg SAPF is achieved using three-level three dimensional space vector modulation with balancing strategy based on the effective use of the redundant switching states of the inverter voltage vectors. Complete simulation of the resultant active filtering system validates the efficiency of the proposed nonlinear control method. Compared to the traditional control, the use of feedback linearization control allows to exhibit excellent transient response during balanced and unbalanced load, and grid voltage. Ó 2014 Elsevier Ltd. All rights reserved.

Introduction The excessive use of power electronic equipments, which represent nonlinear loads, in a distribution network has caused many disturbances in the quality of power such as harmonic pollutions, unbalanced load currents, and reactive power problems. As a result poor power factor, weakening efficiency, overheating of motors and transformers, malfunction of sensitive devices etc. are encountered [1–3]. Conventionally, a passive power filter which consists of passive elements is used to provide harmonic filtering as an economical and effective filtering device. However it has shortcomings such as fixed compensation performance, bulk in size and resonance troubles [4–7]. Important kinds of passive power filters and their configurations are discussed in [4]. To overcome the shortcomings of passive power filters and to mitigate the power pollution in networks caused by the nonlinear loads, an active power filter (APF) was established in around 1970s [8–10]. APFs are previously not implemented in power networks, because of unavailability of high speed power switching devices. Recently the power electronic ⇑ Corresponding author at: Département de l’Electronique et des Communications, Faculté des Nouvelles Technologies d’Information et Communication, Université Kasdi Merbah, Ouargla 30000, Algeria. Tel.: +213 661352139. E-mail addresses: [email protected] (M. Bouzidi), [email protected] (A. Benaissa), [email protected] (S. Barkat). http://dx.doi.org/10.1016/j.ijepes.2014.03.071 0142-0615/Ó 2014 Elsevier Ltd. All rights reserved.

development spurred the interest in IGBTs, MOSFETs, etc. [8] and then APFs are developed incorporating power electronics technology to support the needs of industry. Shunt, series, and hybrid configuration are the three main types of three-phase, three-wire active power filters and their merits and demerits are discussed in [4]. For medium to high power applications the multilevel converters are the most attractive technology. Indeed, multilevel converters have shown some significant advantages over traditional two-level converters [9–12]. The main advantages of the multilevel converter are a smaller output voltage step, lower harmonic components, a better electromagnetic compatibility, and lower switching losses [9–12]. In the recent time, the use of multilevel inverters is prevailing in medium-voltage active power filters without using a coupling transformer [13–17]. In several areas, power is distributed through three-phase fourwire system and traditional APF is inadequate for harmonics compensation and power factor correction. To overcome this shortage, a three-phase four-wire SAPF has been introduced in the 1980s [18–22]. Basically there are two main kinds of three-phase, four-wire SAPF depending on their connection to the neutral wire. In the first kind the neutral wire is connected to the midpoint of the DC-link capacitors. In [23,24], this approach was studied where the inverter was operating as an active power filter. However, although it is simple in terms of topology, this approach is not suitable for SAPF

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application, for the following reasons [25,26]: (1) insufficient DClink utilization, (2) high ripple on DC-link capacitors, (3) problem of DC-link capacitor voltages balance. In the second type the neutral wire is connected to the additional fourth leg, this topology has been shown to be a solution for inverters operating in three-phase four-wire systems and it offers full utilization of the DC-link voltage and lower stress on the DC-link capacitors [26]. Various control strategies have been proposed to control gridconnected DC/AC converters, a classic control usually based on grid voltage [27,28] or virtual-flux [29] oriented vector control (VOC or VFOC) scheme. This scheme decomposes the AC current into active and reactive power components in the synchronously rotating reference frame. Decoupled control of instantaneous active and reactive powers is then achieved by regulating the decomposed converter currents using proportional integral (PI) controllers. One main drawback for this control method is that the performance highly relies on the completeness of current decoupling, the accurate tuning of PI parameters, and the connected grid voltage conditions. Based on the principles of the well-known direct torque control (DTC) [30,31] of AC machines, an alternative control approach, namely, direct power control (DPC) was developed for the control of grid-connected voltage-sourced converters [32,33]. Similar to the traditional DTC, lookup table direct power control (DPC-LUT), as the name indicates, selects the proper converter switching signals directly from an optimal switching table on the basis of the instantaneous errors of active and reactive powers, and the angular position of converter grid voltage [33] or the virtual flux vector. This later result from the integration of converter grid voltage measured with voltage transducers [34] or estimated based on the DClink and the converter switch states [34]. The main disadvantage of DPC-LUT is the variation of switching frequency, which generates an undesired broadband harmonic spectrum range and makes it pretty hard to design a line filter. These disadvantages can be effectively overcome by using space vector modulation (SVM) algorithm to replace the traditional switching table. The combination of SVM and traditional DPC forms the space vector modulation direct power control (SVM–DPC) [35]. Indeed the traditional two dimensional SVM algorithms only can be used to control converter connected to power system with balanced voltage/current where the homopolar component in Concordia transformation is equal to zero. In the four-wire system distribution, the case of unbalanced voltage is taken in consideration; therefore, the homopolar component is not equal to zero. Thus, three dimensional space vector modulation (3DSVM) algorithms must be taken into account in order to generate the desired signal. In [25,26], 3DSVM schemes are analyzed for a four-leg twolevel voltage source inverter. Authors in [23,24] have presented a modulation scheme for a three-level inverter as an active power filter in three-phase four-wire systems where hysteresis modulation was designed in a three-dimensional domain. However, 3DSVM for a four-leg three-level inverter has not yet been studied in stationary reference frame. A novel algorithm of space vector modulation for a four-leg three-level inverter is proposed in this paper. The effectiveness of the proposed modulation algorithm, and the advantages of the proposed topology over conventional ones, are discussed and verified with simulation results with SAPF system. Commonly, the abovementioned control techniques are based on traditional PI control. In order to improve the performance of three-phase four-leg SAPF, various nonlinear control strategies have been reported in the literature. The proposed control strategies include among others sliding mode control [36], passivity control [37], nonlinear optimal predictive control [38] and H1 control [39].

In this paper, a nonlinear control strategy based on the feedback linearization associated to hybrid direct power/current control with 3DSVM (DP/CC-3DSVM) is applied to three-phase three-level four-leg SAPF in order to improve its performances. It is well known that feedback linearization technique is a control method which aims to eliminate the nonlinearity of the system by using the inverse dynamics [40]. It has been applied successfully to control the three-level neutral point clamped (NPC) boost converter [41], three-phase AC/DC PWM converters [42] and three-level three-phase shunt active power filter [43]. As a result, good performances have been reported and the nonlinear control law was able to reduce the influence of parametric variations, utility disturbances, and DC load shedding [41]. This paper is organized as follows. In Section ‘Four-leg shunt active power filter’, the configuration of four-leg SAPF is presented and the system model is developed. In Section ‘Control of threelevel four-leg compensator’, the feedback linearization associated to the DP/CC-3DSVM is investigated. The nonlinear controllers are synthesized and the three-level 3DSVM with balancing capability are presented also in this section. In Section ‘Simulation results’, the performances of controlled system are verified by simulation results. Finally, in Section ‘Conclusion’ some conclusions are established. Four-leg shunt active power filter System description The basic compensation principle of the four-leg SAPF is shown in Fig. 1. The main task of the four-leg SAPF is to reduce harmonic currents and to ensure reactive power compensation. Ideally, the four-leg SAPF needs to generate just enough reactive and harmonic current to compensate the nonlinear load harmonic in the line. The resulting total current drawn from the AC main is sinusoidal and balanced. The compensated neutral current is provided through a fourth leg allowing a better controllability than the three-leg with split-capacitor configuration. The main advantage of the four-leg configuration is the ability to suppress the neutral current from the source without any drawback in the filtering performance. Mathematical model of the three-level four-leg SAPF The switching functions are defined as Fij where i e {a, b, c, n} is the phase and j e {0, 1, 2}is the voltage level. Fij takes value ‘‘1’’ if iphase is connected to voltage level j and ‘‘0’’ otherwise; these switching functions can be expressed as:

F x2 ¼ Sx2 Sx1 F x1 ¼ Sx2 Sx1

x ¼ a; b; c or n

ð1Þ

F x0 ¼ Sx2 Sx1 The instantaneous AC converter phase to neutral voltages vFa, vFb and vFc can be expressed in terms of switching functions and DC-link voltages capacitors as given by:

2

3

2

v Fa F a2  F n2 6 7 6 4 v Fb 5 ¼ 4 F b2  F n2 v Fc F c2  F n2

32

3

v C2 þ v C1 76 F c0  F n0 54 v C1 75

F a1  F n1

F a0  F n0

F b1  F n1 F c1  F n1

F c0  F n0

ð2Þ

0

The mathematical equations which govern the behavior of the AC-side of SAPF are:

diFa 1 ¼ ðv Fa  v a  RF iFa Þ LF dt diFb 1 ¼ ðv Fb  v b  RF iFb Þ LF dt diFc 1 ¼ ðv Fc  v c  RF iFc Þ LF dt

ð3Þ

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PCC vsa

R sa

vsb

R sb

vsc

R sc

L sa

i sa

Lsb

va

i sb

L sc

vb

i sc

iLa

R La

L La

iLb

R Lb

L Lb

Nonlinear

iLc

R Ln

L Lc

Load

vc i sn

i2

iLn

i Fn

i Fc

i Fb

i Fa

S 1a

S 1b

S 1c

S 1n

S 2a

S 2b

S 2c

S 2n

iC 2 L Fa

R Fa

R Fb

L Fb

R Fc

L Fc

vC 2

C2

v Fa

i0

v Fb

vdc

iC 1 v Fc C1 S 1a

S 1b

S 1c

S 1n

S 2a

S 2b

S 2c

S 2n

vC1

i1

Fig. 1. Three-level four-leg SAPF configuration.

where v a ; v b and v c are the point of common coupling (PCC) voltages, iFa ; iFb and iFc ; v Fa ; v Fb and v Fc represent AC side currents and voltages of the SAPF, respectively. Assuming C1 = C2 = C, the DC side of the filter can be expressed as:

dv dc i1  i2 ¼ dt C

Assuming the modulation algorithm will balance voltages in capacitors (vC1 = vC2 = vdc/2), the DC side dynamic equation can be written as follows:

dv dc pdc ¼ dt C eq v dc

ð4Þ

i1 and i2 are the DC-side intermediate branch currents.

vsa vsb

where pdc is the DC active power, and Ceq = C/2.

i sa

Ls

Rs

ð5Þ

i La

va Rs

Ls

i sb

Rs

Ls

i sc

Rl1 Ll 1

i Lb

vb vsc

Rl 2 Ll 2

i Lc

vc

Rl 3 Ll 3

i Ln

i sn i Fa

RF

LF

v Fa

i Fb

RF

LF

v Fb

i Fc

RF

LF

v Fc

C2

v dc C1

i Fn

i Labc

v abc

3

3

abc

abc

i Lo

v αβ

2

i Fabc

8

v C1

S abcn v dc*

abc

αβ

αβ o i L αβ

3

v C2

αβ o i Fo

2

2

v C2

i F αβ * v F* α v F β

* v Fo

pdc* pL

i Fo* = i Lo

i Fo

pF qF 2

qL p~L pdc* Fig. 2. Nonlinear control scheme of direct power/current control for three-level four-leg SAPF.

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(a)

(b)

o

2220

3vdc

Prism 4 2220

Prism 2

Prism 3

2210

Prism 1 2110

2210

2210 2200

2210 1220

1

5v dc 2 3

2120

1210 2110 1120

2211 1100

2100 2221

3vdc 2

1110

0120

0200 1100

2000

2121 1010 2201

0020 1211 0100

0221

2111 1000

1121 0010

2211 1100

β

2111 1000

4

v dc 2 3

5

2212 1101

5

2222 1111 0000

0121

α 2101

1021

0201

2212 1101

2212 1101

0201 0111

2222 1111 0000

2212 1101

1212 0101

0222

1122 0011

2022 1202

0122 1022

8 1102

0202

1102 2002 −2 v dc 3

0112 1012

0102

2102

2112 1001

2102

7

1102 2112 1001

2102

2002

2112 1001

1002

2112 1001

2102

7 Tetrahedrons

2102

8

1102

2112 1001 1002

1102

8 Tetrahedrons

9

−5vdc 2 3

1102

10 1002

0002

− 3v dc

2002

2102

7 2102

2001

6

2112 1001

1002 1002

0012

1112 0001

1112 0001

0022

2212 1101 2102

7 Tetrahedrons

1112 0001

2012

6

1102

− 3 vdc 2

1112 0001

2212 1101

2212 1101

2102

5

2101

7 2112 1001

1112 0001

0212

2112 1001

7

−v dc 3

2112 1001

2202

2001

2112 1001

2112 1001

6

2001

2101

2112 1001

2101 2112 1001

2101

2202

2212 1101

2222 1111 0000

2202

0021

2202

2212 1101

6 2001 −vdc 2 3

2122 1011

2111 1000 2212 1101

2101

5

2212 1101 2212 1101

4

2001 2101

2111 1000

2101

2101

2222 1111 0000

2101

2111 1000

2201

2111 1000

2101

2111 1000

2101

2000

3

2111 1000

3

2211 1100 2101

2101 2111 1000

2211 1100

2212 1101

2021 1201

0211

2100 2111 1000

4

4

2111 1000 2211 1100

2222 1111 0000

2201

2

2111 1000

2

2100

3

2000

2100 2111 1000

2100

2201

2211 1100

2221 1110

vdc 3

2201

2211 2211 1100 1100

3

2211

1221 0110

2110 2211 1100

2221 1110

2010 1020

2

2110

2110

2211 1100

2221 1110

0210

2100 2211 1100

2211 1100

2

2020 1200

2000

2100

2200

2221 1110

2 vdc 3

2100

1

2110

2100

2110 2210

2200

0220

1

1

0002

10 Tetrahedrons Fig. 3. Three dimensional representation, (a) Switching voltages vectors in abo coordinates, (b) tetrahedrons in the first sector.

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Based on the Concordia coordinates transformation, the differential equations describing the dynamic model of the four-leg SAPF in abo reference frame are given by (6)

diF a 1 ¼ ðv F a  v a  RF iF a Þ LF dt diFb 1 ¼ ðv Fb  v b  RF iFb Þ LF dt diFo 1 ¼ ðv Fo  v o  RF iFo Þ LF dt dv dc pdc ¼ dt C eq v dc

ð6Þ

power qF. In order to ensure that each of the previously mentioned  outputs follows its reference (v dc ; iFo ; pF andqF respectively), it is appropriate to divide the system (6) into two subsystems: Subsystem 1: The first subsystem is described by the following equation:

diF a 1 ¼ ðv F a  v a  RF iF a Þ LF dt diFb 1 ¼ ðv Fb  v b  RF iFb Þ LF dt diFo 1 ¼ ðv Fo  v o  RF iFo Þ LF dt

ð11Þ

When the first subsystem is expressed in the form of (12):

x_ ¼ f ðxÞ þ gðxÞu

Control of three-level four-leg compensator The basic operation of the proposed control method is shown in Fig. 2. The nonlinear loads are constructed from three uncontrolled single-phase rectifiers. The capacitor voltage is compared with its reference value v dc , in order to maintain the energy stored in the capacitor constant. The proposed nonlinear controller is applied to regulate the error between the capacitor voltage and its reference. The output of nonlinear voltage controller presents the reference of DC active power pdc . The compensating powers are compute using the instantaneous p–q theory, and the reference  of the homopolar current iFo is chosen equal the homopolar component of the nonlinear load current [35]. The alternate value of active power is extracted using high-pass filter (HPF). The output signals from nonlinear power and current controller are used for switching signals generation by a 3DSVM.

ð12Þ

It results:

3  RLFF x1  L1F v F a 6 7 6 7 RF 1 7 f ðxÞ ¼ 4 f2 5 ¼ 6 4  LF x2  LF v Fb 5 f2  RLFF x3  L1F v Fo 2

f1

21 L

6 F gðxÞ ¼ 6 40 0

2

3

0 1 LF

0

0

3

7 07 5

1 LF

(a)

p–q Theory based control strategy 500



pL qL



 ¼

v a v b  iLa  v b v a iLb

ð7Þ

The instantaneous active and reactive powers include AC and DC values and can be expressed as follows:

L þ p ~L pL ¼ p ~L þ q ~L qL ¼ q

vFo*

Instantaneous active and reactive powers of the nonlinear load are computed as:

-500 1000 500

ð8Þ

0

vFβ*

L Þ of the pL and qL are the average active and L ; q DC values ðp reactive power originating from the positive-sequence component ~L Þ of the pL and qL are ~L ; q of the nonlinear load current. AC values ðp the ripple active and reactive powers [44]. For harmonic, reactive power compensation and balancing of unbalanced three-phase load currents, all of the reactive power L and q ~L components) and harmonic component p ~L of active power (q are selected as compensation power references as follows [44]:

pF qF



 ¼

~L  pdc p

1000

ð9Þ

-800

Model subdivision There are four outputs to be controlled: DC capacitor voltage vdc, homopolar current component iFo, active power pF, and reactive

-500

vFα *

(b)

0

 iFo

Feedback linearization control

-1000

1500

200

-200

ð10Þ

-1500

1000

400

The signal pdc is used as an average real power and is obtained from the nonlinear DC voltage controller. Since the zero-sequence current must be compensated the reference of homopolar current is given as:

¼ iLo

-1000

500

600



qL

-500

0

800

vFβ*



0

-400 -600

-1000 -1500

-1000

-500

0

500

1000

1500

vFα * Fig. 4. Trajectory of reference voltage vector under unbalanced sinusoid condition with conventional algorithm (a) trajectory in 3-dimensional space; (b) projection of the trajectory on ab plan.

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M. Bouzidi et al. / Electrical Power and Energy Systems 61 (2014) 629–646

2

(a)

U *

500

Fo

iF a

3

2

u1

3

2

3

Table 2 Interchanging the switching states in odd sectors.

-500 1500 1500

1000

1000 500

500 0

UFβ *

0

U * Fα

-500

Sector 1

Sector 3

Sector 5

a b c n

a?b b?c c?a n?n

a?c b?a c?b n?n

(b) Table 3 Interchanging the switching states in pair sectors.

1200 1000 800

U Fo*

2

Subsystem 2: The second subsystem is defined by Eq. (5), which has only one state x = vdc and only one control input u = pdc. The second subsystem can be also written in the form (12).

0

1400

3

v Fa 6 7 6 7 6 7 6 7 x ¼ 4 x2 5 ¼ 4 iFb 5; u ¼ 4 u2 5 ¼ 4 v Fb 5 x3 u3 v Fo iFo x1

600

Sector 2

Sector 4

Sector 6

a b c n

a?b b?c c?a n?n

a?c b?a c?b n?n

400 v F*

200

0 -600

-400

-200

0

200

400

600

800

1000

1200

U Fα *

No

Yes

Fig. 5. Trajectory of reference voltage vector under unbalanced sinusoid condition with proposed algorithm (a) trajectory in 3-dimensional space; (b) projection of the trajectory on ab plan.

No

Yes

Yes

No

U F*

β 2nd Sector 020x

220x

120x

PR

2 3

2 1

PR PR

121x 010x U

2 2

221x 110x

PR 42 U *1

Fβ2

* Fβ

PR 41

UF*

PR 21

UF*1α1 U F*α

210x

PR11

ψ

222x 111x 000x

1st Sector

PR31

211x 100x

α

abcx 200x

Fig. 6. Space voltage vectors for a three-level four-leg inverter in sector one and two.

Table 1 Prism identification in each sector k (k = 1or 2). l1

k

l2

k

PRki

0

0

PRk4 ðifU k F1 PRk2 ðifU k F1 PRk1 PRk3

1

0

0

1

Where PRki is a prism number i located in sector k.

=2

þ þ

U k F2 U k F2

=1

< 1Þ P 1Þ

Fig. 7. Schematic diagram of the 3DSVM with proposed algorithm and balancing DC capacitors voltages.

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M. Bouzidi et al. / Electrical Power and Energy Systems 61 (2014) 629–646 

Where

f ðxÞ ¼ 0; gðxÞ ¼

v ¼ kðv dc  v dc Þ þ

1 C eq v dc

ð17Þ

where k is a positive constant.

DC voltage controller synthesis The synthesis of the DC voltage controller is based on the second subsystem. The derivative of the output y = vdc is given by:

y_ ¼ Lf hðxÞ þ Lg hðxÞu

ð13Þ

where Lfh stands for the Lie derivative of h with respect to f, similarly Lgh.Then:

y_ ¼

dv dc dt

pdc

ð14Þ

C eq v dc

Power and current controller synthesis The outputs of the first subsystem are selected as:

y1 ¼ pF y2 ¼ qF And their derivatives are given by:

d ½y dt 1

The control input pdc appears in (14), so the relative degree is r = 1. The relative degree of this output is equal to the order of subsystem 2, which corresponds clearly to an exact linearization [40]. Then the control law is obtained by:

y2

y3 T ¼ fðxÞ þ DðxÞu

ð19Þ

(a) 50

i sa (A)

pdc ¼ C eq v dc v

ð18Þ

y3 ¼ iFo

ð15Þ

where

0

-50

y_ ¼ v

ð16Þ

For a problem of tracking of trajectory defines by term v is expressed by:

v

 dc ðtÞ,

0.3

0.305

0.31

0.315

0.32

Time (s)

the

(b) Table 4 System parameters. RMS value of phase voltage

220 V

DC-link capacitor C1, C2 Source impedance Rs, Ls Filter impedance RF, LF Line impedance RL, LL DC-link voltage reference Diode rectifier load Rl , Ll Switching frequency fs Sampling frequency k, k1 = k2 = k3 constants

5 mF 0.01 mX, 1 mH 0.01 mX, 1 mH 0.01 mX, 1 mH 800 V 5 X, 10 mH 5 kHz 1 MHz 50, 8  105

v dc

Fig. 9. (a) Source current after harmonics compensation using nonlinear controller, (b) Its harmonic spectrum.

where

(a) 50 isa (A)

isa (A)

(a) 50 0

-50

-50 0.3

0

0.305

0.31

0.315

0.4

0.32

(b)

Fig. 8. (a) Source current before harmonics compensation, (b) Its harmonic spectrum.

0.405

0.41

0.415

Time (s)

Time (s)

(b)

Fig. 10. (a) Source current after harmonics compensation using PI controller, (b) Its harmonic spectrum.

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M. Bouzidi et al. / Electrical Power and Energy Systems 61 (2014) 629–646

2 va

3

2

v a f1 þ v b f2 7 6 6 fðxÞ ¼ 4 v b f1  v a f2 7 5; f3

vb

LF

LF

6 6v DðxÞ ¼ 6 LFb 4 0

 vLFa 0

0

3

outputs is equal to the order of subsystem 1, than it is about of an exact linearization [40]. The decoupling matrix determinant is different to zero, and then the control law is given as:

7 7 07 5

1 LF

2

The control inputs appear in (19). In this case, the relative degree is r = r1 + r2 + r3 = 3. The relative degree of the chosen

(a) Source currents i sabc (A)

Without SAPF

3

2

Balanced load

With SAPF

Unbalanced load

-50 0

0.1

0.2

0.3

0.4 Time (s)

0.5

0

0

-50

-50 0.17

0.18

0.19

0.2

0.6

0.7

0.8

Zoom 50

Load currents i Labc (A)

ð20Þ

0

50

(b)

33

50

Zoom

0.16

2

v1 6 7 6 6 77 u ¼ 4 u2 5 ¼ DðxÞ1 4fðxÞ þ 4 v 2 55 u3 v3 u1

0.21

0.22

0.23

0.24

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

100

0

-100 0

0.1

0.2

0.3

0.4 Time (s)

0.5

0.6

0.7

0.8

0.7

0.8

Zoom

100 50 0 -50 -100

Fabcn

SAPF courrents i

(c)

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

(A)

0.46

i

i

Fa

50

i

Fb

i

Fc

Fn

0 -50 0

0.1

0.2

0.3

0.4 Time (s)

0.5

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Zoom 50

0

-50 0.46

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Fig. 11. Simulation results of the proposed DP/CC-3DSVM using nonlinear controller.

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The application of the linearization law on the first subsystem led to two decoupled linear systems, given by:

v1 3 6_ 7 6 7 4 y2 5 ¼ 4 v 2 5 v3 y_ 3

2

ð21Þ

ð22Þ

 Fo

where k1, k2 and k3 are positive constants.

Neutral current isn (A)

(d)

 F

v 1 ¼ k1 ðpF  pF Þ þ dpdt v 2 ¼ k2 ðqF  qF Þ þ dqdt v 3 ¼ k3 ðiFo  iFo Þ þ didt

 F

20

0

-20 0

0.1

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0.3

0.4

0.5

0.6

0.7

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Time (s)

Zoom 20 10 0 -10 -20 0.16

(e) Source power ps (W) and qs (Var)

x 10

0.17

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4

3 2 1 0 -1 0

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Time (s)

(f) DC voltage and its reference (V)

3

900 850 800 750 700 0

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0.4

Time (s)

(g) DC capacitors voltages (V)

y_ 1

450

400

350 0

0.1

0.2

0.3

0.4

Time (s)

(h)

va (V) and i sa (A)

2

The control law used for tracking is:

200 0 -200 0.3

0.31

0.32

0.33

Time (s) Fig. 11 (continued)

0.34

0.35

0.36

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Three dimensional space vector modulation In a three-level three-legged converter, there are 33 possible switch combinations. With the fourth neutral leg, the total number of combinations is 34. The switch combinations are represented by ordered sets (SaSbScSn). Where

8 > < Sa ¼ 2 if F a2 ¼ 1 Sa ¼ 1 if F a1 ¼ 1 > : Sa ¼ 0 if F a0 ¼ 1

ð23Þ

The same notation applies to phase legs b and c and the fourth neutral leg. For switching combinations, the vectors given by transforming (2) to abo coordinates, can be described using a graphical representation in three-dimensional space as shown in Fig. 3a. There are three zero switching vectors (2222, 1111, 0000), and 65 unique non-zero switching vectors. It can be viewed as that each of the switching vectors for a three-legged converter splits into three switching vectors, depending on switch position of the neutral leg. All the 81 switching vectors can be sorted into thirteen layers. The diagram of space vectors can be divided into six sectors with every sector further divided into four prisms. As shown in Fig. 3b, the prisms 1 and 3 are formed by 7 tetrahedrons, while the prisms 2 and 4 are formed by 8 and 10 tetrahedrons respectively. In each tetrahedron, three tasks must be done: localization of the reference voltage vector v F , calculation of duration time intervals of adjacent switching vectors, and the generation of the corresponding pulses. This increases the required computational time and augments the hardware and software complexity.

Proposed 3DSVM algorithm The proposed algorithm can reduce remarkably the complexity of 3DSVM by using two sectors only (sector one and sector two) in the conception of all modulation algorithm steps such as: determination of the space vector location, duration time calculation, and pulses generation. The six sectors are divided into two identical groups, odd sectors (1, 3 and 5) and pair sectors (2, 4 and 6). The reference voltage vector usually turns in the space abo and crosses all the sectors (Fig. 4), then, it is necessary to build another vector U F which turns only in sectors 1 and 2 and takes all information about v F in the other sectors, as shown in Fig. 5. The components of new reference voltage vector are:

U F a ¼ U F ab cosðwÞ U Fb ¼ U F ab sinðwÞ U Fo

¼v

ð24Þ

 Fo

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 where U F ab ¼ v 2 F a þ v Fb and w = mod(h, 2p/3) mod(x,y): is a function which gives the division remainder of x on y, w and h are the angles of the vectors U F and v F projected in ab plane respectively. The angle h given by:

h ¼ tan 21



v Fb  v F a

ð25Þ

And: tan 21: is a function returns the four-quadrant inverse tangent. Determination of the space vector location. The space vector location is determined in three steps: (1) determining the sector number of where the vector lies, (2) determining the number of prisms, and (3) determining the tetrahedron number of where the reference vector located.

SAPF voltage VFa (V)

(i) 1000

0

-1000 0

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0.8

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Time (s)

SAPF voltage VFb (V)

(j) 1000

0

-1000 0

0.1

0.2

0.3

0.4

Time (s)

SAPF voltage VFc (V)

(k) 1000

0

-1000 0

0.1

0.2

0.3

0.4

Time (s) Fig. 11 (continued)

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Steps one and two are similar to those of three-level 2DSVM [45,46]. Step 1: Sector number computation. The sector numbers are given by [46]:



 h 2 f1; 2; 3; 4; 5; 6g p=3

Source currents i sabc (A)

(a)

ð26Þ

Step 2: Prisms identification Reference vector U F is projected on the axes of 60° coordinate system [45]. In sector one and two, the normalized projected comk ponents are U k F1 and U F2 given by (27) (k e {1, 2} for sector one or two). Fig. 6 shows the projection of U F in the first sector.

50 0 -50 0

0.1

0.2

0.3

0.4

0.5

50

50

0

0

-50

-50

Load currents i

Labc

(b)

0.17

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0.22

0.23

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0.24

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0.8

Zoom

0.47

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0.5

0.51

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0.53

(A)

0.16

0.6

Time (s)

Zoom

100 0 -100 0

0.1

0.2

0.3

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0.8

Time (s)

Zoom

100 50 0 -50 -100

Fabcn

(c)

0.47

0.48

0.49

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0.53

0.54

(A)

0.46

SAPF courrents i

s ¼ ceil

where ceil is the C-function that adjusts any real number to the nearest, but higher, integer.

i

i

Fa

50

i

Fb

i

Fc

Fn

0 -50 0

0.1

0.2

0.3

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0.6

Time (s)

Zoom

100 50 0 -50 -100 0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

Fig. 12. Simulation results of the proposed DP/CC-3DSVM using PI controller.

0.54

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M. Bouzidi et al. / Electrical Power and Energy Systems 61 (2014) 629–646 U

2 v dc 3 2

 p2ffiffi U 3 F ab

ð27Þ

sinðw  ðk  1Þ p3Þ qffiffi

(d)

Natural current i sn (A)

2 v dc 3 2

k

l1 ¼ intðU k F1 Þ

ð28Þ

k

l2 ¼ intðU k F2 Þ

40 20 0 -20 -40 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Time (s)

Zoom

40 20 0 -20 -40 0.16

(e) Source powers ps (W) and qs(Var)

x 10

0.17

0.18

0.19

0.2

0.21

0.22

0.23

0.24

4

4 2 0 -2 0

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0.4

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0.8

Time (s)

DC voltage and its reference (V)

(f)

900 850 800 750 700 0

0.1

0.2

0.3

0.4

Time (s)

(g) DC capacitors voltages (V)

U k F2 ¼

In order to identify the prism where the required reference voltage vector is located, the following integers are used:

U F ab cosðw  ðk  1Þ p3ÞÞ  pF affiffi3b sinðw  ðk  1Þ p3 Þ qffiffi

450 v

C2

v

C1

400

350 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Time (s)

(h)

vsa (V) and i sa (A)

U k F1 ¼

400 200 0 -200 -400 0.3

0.31

0.32

0.33

Time (s) Fig. 12 (continued)

0.34

0.35

0.36

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M. Bouzidi et al. / Electrical Power and Energy Systems 61 (2014) 629–646

where the int() function returns the nearest integer that is less than or equal to its argument. The prism number is obtained according to k k the value of l1 and l2 , as shown in Table 1. Step 3: Tetrahedron identification After the selection of prism, the next step is to determine the tetrahedron according to the location of the reference voltage. As shown in Fig. 3, each tetrahedron is limited from the top and the bottom by two planes. Each plane is created by three switching vectors. For example, the localization condition of tetrahedron 1 in the prism 1 of the first sector numbered as TeT k;i j (k = 1 for sector 1, i = 1 for prism 1 and j = 1 for tetrahedron 1) is given by:

rffiffiffi 3 U Fo 6 U F a þ v dc 2 pffiffiffi  3  U U Fo > F a þ U 2 2 Fb

ð29Þ

Duration time calculation. In order to minimize the circulating energy and to reduce the current ripple, switching vectors adjacent to the reference vector should be selected. At any sampling instant the tip of the voltage vector lies in a tetrahedron formed by the four switching vectors adjacent to it. The on-duration time intervals of each vector are obtained in accordance to the average value principle, which is given by [45,46]:

v 1 t1 þ v 2 t2 þ v 3 t3 þ v 4 t4 ¼ UF T s

ð30Þ

t1 þ t2 þ t2 þ t4 ¼ T s

(i)

SAPF voltage VFa (V)

where Ts is the switching period, v1, v2, v3 and v4 are the four switching vectors adjacent to the reference voltage vector, and t1, t2, t3 and t4 are their calculated on-duration time intervals respectively. Expression (30) can by decomposed in the abo coordinates system as follows:

2

32

3

3

2

v 1a v 2a v 3a v 4a t1 U F a T s 7 7 6 6 v 2b v 3b v 4b 76 t2 7 6 UFb T s 77 76 7 ¼ 6 7 v 2o v 3o v 4o 54 t3 5 4 UFo T s 5

6v 6 1b 6 4 v 1o 1

1

1

1

t4

ð31Þ

Ts

With a proposed algorithm, the on duration time intervals are calculated only in sector one and sector two. Pulse generation. The final step is to apply the calculated duration time intervals to the corresponding vectors in each tetrahedron. The pulses are generated only in sector one and two, the other sector can deduced by simply interchanging the states of the output phases of pair and odd sectors as given in Table 2 (see Table 3). In appendix’s table an equivalence between switching states of each tetrahedron located in same prism for sectors one and two can be observed. Based on this equivalence, the generation of the pulses in all tetrahedrons located in same prism is not necessary. For example there are seven tetrahedrons in prism one located in sector one, the pulses are generated only in four tetrahedrons, as given in appendix’s table. DC-capacitor voltages balancing based on minimum energy property In the three-level three-leg three-wire NPC topology, the balancing problem of the DC-link voltage can be solved using the redundant vectors due to their effect on the DC-link capacitors voltage [45,46]. This paper shows clearly that the balancing problem of the DC-link voltage in the three-level four-leg topology can be solved using the redundant vectors in a similar way. The electrical energy stored in the chain of DC-link capacitors is given by:



C 2 ðv þ v 2C2 Þ 2 C1

ð32Þ

When all capacitor voltages are balanced, the total energy E reaches  its minimum of Emin ¼ C v 2 dc =4, with v dc is the desired value of DC

1000

0

-1000 0

0.1

0.2

0.3

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0.5

0.6

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(j)

SAPF voltage VFb (V)

Time (s) 1000

0

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(k)

SAPF voltage VFc (V)

Time (s) 1000

0

-1000 0

0.1

0.2

0.3

0.4

Time (s) Fig. 12 (continued)

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voltage [43]. This condition is called the minimum energy property which can be used as the basic principle for DC-capacitor voltages balancing and control [45]. The adopted control method should minimize the quadratic cost function J associated with voltage deviation of the DC-capacitors. The cost function is defined as follows:



iC1 ¼ i1

C ðDv 2C1 þ Dv 2C2 Þ 2

ð33Þ

where

ð35Þ

iC2 ¼ i1 þ i0

By substituting iC2 and iC1 given by (35) in (34), the condition to achieve voltage balancing is deduced as:

Dv Cj ¼ v Cj  v dc =2; j ¼ 1; 2

Dv C1 i1 þ Dv C2 ði1 þ i0 Þ 6 0

The mathematical condition to minimize J is:

dJ ¼ Dv C1 iC1 þ Dv C2 iC2 6 0 dt

ð34Þ

where iCj (j = 1, 2) is the current through capacitor Cj. These currents are affected by the DC-side intermediate branch currents, i0 and i1.

ð36Þ

When the DC link voltages vC1 and vC2 are close to their reference v dc =2, the following condition is verified :

Dv C1 þ Dv C2 ¼ 0

ð37Þ

400

Source voltages (V)

(a)

These currents can be calculated if the switching states used in the switching pattern are known. Thus, it is advantageous to express (34) in terms of i0, and i1. The DC-capacitor currents are expressed as:

200 0 -200 -400 0

0.05

0.1

0.15

0.2

0.25

0.3

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0.2

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0.2

0.25

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0.35

(b)

Source currents isabc (A)

Time (s)

50 0 -50 0

0.05

0.1

0.15

(c)

Load currents i Labc (A)

Time (s)

50

0

-50 0

0.05

0.1

0.15

Time (s)

(d)

i

SAPF currents i Fabcn (A)

40

i

Fa

(d)

Fb

i

i

Fc

Fn

20 0 -20 -40 0

0.05

0.1

0.15

Time (s)

10 5 0 -5 -10 -15

x 10 4

(f)

15

Source powers ps (W) and q s (Var)

Neutral current i sn (A)

(e)

3 2 1 0

0

0.05

0.1

0.15

0.2

Time (s)

0.25

0.3

0.35

0

0.05

0.1

0.15

0.2

0.25

Time (s)

Fig. 13. Simulation results of the proposed DP/CC-3DSVM using nonlinear controller under unbalanced grid voltage.

0.3

0.35

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Using (37), Eq. (36) can be written as:

Dv C2 i0 6 0

ð38Þ

Applying the averaging operator, over one sampling period, to (38) results in:

Z

ðkþ1ÞT s

ðDv C2 i0 Þdt 6 0

ð39Þ

kT s

Assuming that sampling period Ts, is adequately small as compared to the time interval associated with the dynamics of capacitor voltages. These letter can be assumed to remain constant over one sampling period [45] and (39) is consequently simplified to:

Dv C2 ðkÞi0 6 0

ð40Þ

(a)

Source voltages (V)

where DvC2(k) is the voltage drift at sampling period k, and i0 is the averaged value of the i0.

Simulation results For verifying the validity of the proposed control of the threelevel four-leg SAPF; and due to lack sufficient hardware in our laboratory to implement this complexe control, computer simulations under different load and source voltage conditions are carried out on the MATLAB/Simulink. The simulation parameters are shown in Table 4.

400 200 0 -200 -400 0

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(b)

Source currents i sabc (A)

Time (s)

50 0 -50 0

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0.1

0.15

(c)

Load currents i Labc (A)

Time (s)

50

0

-50 0

0.05

0.1

0.15

(d)

SAPF courrents i Fabcn (A)

Time (s)

i

i

Fa

50

Fb

i

i

Fc

Fn

0

-50 0

0.05

0.1

0.15

(e)

15

Neutral current i n (A)

Time (s)

10

(f)

5 0 -5 -10 -15

0

0.05

0.1

0.15

0.2

Time (s)

0.25

0.3

0.35

Source powers p s (W) and qs (Var)

1 Ts

The relationship between the DC-intermediate branch current i0 and AC-currents (iFa, iFb and iFc) for different switching states is required. The current i0 should be computed for different combinations of adjacent redundant switching states over a sampling period and the best combination which minimizes (40) is selected. The implementation procedure of the 3DSVM with proposed algorithm and voltage balancing strategy is summarized in Fig. 7.

x 10 4 3 2 1 0 0

0.05

0.1

0.15

0.2

Time (s)

Fig. 14. Simulation results of the proposed DP/CC-3DSVM using PI controller under unbalanced grid voltage.

0.25

0.3

0.35

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Fig. 15. Frequency spectrum of source current, (a) using nonlinear controller, (b) using PI controller.

10 8

THD (%)

PI controller 6

Nonlinear controller

4 2 0

2

4

6

8

10

Switching frequency f s (kHz) Fig. 16. Source current THD versus value of switching frequency.

DC capacitors voltages ripples (%)

The source current of the first phase and its harmonic spectrum before and after compensation are illustrated in Figs. 8–10. It results that the SAPF decreases the total harmonic distortion (THD) in the source currents from 17.08% to 2.77% with PI controller. However, with nonlinear controller, the THD is reduced to 0.22% which proves the effectiveness of the proposed nonlinear controller. Figs. 11 and 12 present the dynamic behavior of the system for nonlinear and PI controller respectively, where the four-leg SAPF is switched on 0.2 s later. After 0.5 s, an additional load is added in single-phase diode bridge rectifier in phase (b) in order to induce an unbalanced load. It can be observed that the three-phase source currents are balanced and sinusoidal after compensation in two control methods for this case. As shown in Figs. 11d and 12d, the neutral current is almost canceled with a low ripple in case where the nonlinear control is applied (2.86% for the nonlinear controller and 18.57% for the PI controller). In Figs. 11e and 12e, one can see that the active power joined its nominal value and that the reactive power becomes null when the active filter is activated at time 0.2 s. For clarity, a phase-a of source current and its corresponding phase voltage are shown for illustration in Figs. 11h and 12h. It can be observed that the unity power factor operation is successfully achieved. The DC bus voltage variation due to the load change is about 30 V, and the recovery time of DC voltage is about 0.1 s. The capacitor voltages on the DC bus are balanced before and after the load variation. However, the absence of overshoots in DC voltages responses during nonlinear load change, and low neutral current and power ripples, demonstrates the superiority of the nonlinear controller compared to its counterpart traditional PI controller. The simulation results with the nonlinear and PI controller under unbalanced grid voltages are shown in Figs. 13 and 14 respectively. The neutral current is eliminated and the reactive power compensation is successfully achieved using nonlinear control method. As shown in Fig. 15 the total harmonic distortion in source currents is 3.58% with PI control and 2.85% with nonlinear control. So, the distortion in source current with nonlinear control under unbalanced grid voltage is also less than in case of PI control method. From the Fig. 16, one notices well that the THD decreases remarkably with the increase of the switching frequency. It can be concluded that the DP/CC-3DSVM based on nonlinear controller can operate with reduced switching frequency (1–2 kHz). According to Fig. 17, the ripple of DC capacitors voltages decreases with the increase in the DC voltage value vdc, which leads pffiffiffi consequently to decrease the modulation index ðm ¼ 2U F ab =v dc Þ. Indeed, with a smaller m, the number of redundant switching states increases, which provides a higher degree of freedom to balance the DC capacitors voltages, and consequently, the ripple of these voltages becomes small.

1.2 1 0.8 0.6 0.4 0.2 0

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

DC reference voltage (kV) Fig. 17. DC capacitors voltages ripple versus value of DC voltage.

5. Conclusion This work presented a theoretical study with simulation of hybrid direct power/current control combined with feedback linearization control for a three-level four-leg shunt active power filter. The performances of the active power filtering system based on nonlinear controller are analyzed and compared with conventional controller for different disturbed operating conditions. The proposed control scheme gives high performance under both dynamic and steady state operations in terms of the current harmonics filtering, reactive power compensation, source current balancing, and neutral current elimination. In this paper three-level 3DSVM with a new algorithm is also presented for three-level four-leg converter. The significant outcome of the proposed algorithm is its inherent simplicity. Unlike the conventional 3DSVM algorithm that requires reference vector determination, on-duration time calculation and pulses creation in all sectors. Therefore, the proposed 3DSVM algorithm is much simpler and easier for digital implementation since it reduces the hardware and software complexity and decreases the required computational time. Furthermore, the correction of the inherent instability of the DC link capacitor voltages has been considered. Indeed, the objective of maintaining balanced voltages in DC-link capacitors is carried out effectively with the adopted three-level 3DSVM.

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Appendix Table: Interchanging the switching states of each tetrahedron located in same prism for sector one and two.

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