Local electrical characterization of SOI wafers by scanning probe microscopy

Local electrical characterization of SOI wafers by scanning probe microscopy

Materials Science and Engineering B91– 92 (2002) 156– 159 www.elsevier.com/locate/mseb Local electrical characterization of SOI wafers by scanning pr...

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Materials Science and Engineering B91– 92 (2002) 156– 159 www.elsevier.com/locate/mseb

Local electrical characterization of SOI wafers by scanning probe microscopy Yoshimori Ishizuka *, Takayuki Uchihashi, Haruhiko Yoshida, Seigo Kishino Department of Electronics, Himeji Institute of Technology, Faculty of Engineering, 2167 Shosha, Himeji 671 -2201, Japan

Abstract Cross-sectioned silicon-on-insulator (SOI) wafers were examined by a combination of scanning probe techniques, namely scanning capacitance microscopy (SCM), scanning resistance microscopy (SRM) and Kelvin probe force microscopy (KFM). Tests were conducted using bonded SOI and separation by implanted oxygen (SIMOX) wafers. SCM images identified the depletion layer at the SOI–buried-oxide (BOX) interface, and the thickness of the depletion layer was found to vary according to the bias voltage applied to the Si substrate. SRM images identified the high-resistance region in the SOI wafers, and KFM resolved the charge distribution, revealing that SOI wafers hold inherent positive charge. The locations of positive charge accumulation were found to differ between the two types of SOI wafers. Based on the results of this study, the use of multiple scanning probe techniques represents a promising tool for sub-micron-scale electrical characterization of SOI wafers. © 2002 Published by Elsevier Science B.V. Keywords: Silicon-on-insulator (SOI); Electrical characterization; Scanning probe microscopy; Depletion layer; Fixed positive charge

1. Introduction The importance of silicon-on-insulator (SOI) technology in the large-scale integration (LSI) industry has increased due to the advantages of SOI over bulk-Si LSI technology for low-voltage, -power and high-speed device applications. It is widely considered that the application of SOI technology in the fabrication process will become prevalent in the LSI industry in the very near future. Therefore, the characterization and inspection of electrical properties such as the interface trap density, electric charge and carrier density of thin SOI wafers are very important in ensuring device reliability. In particular, as the scale-down of MOS devices continues to progress, the need for characterization on sub-micron and nanometer scales will steadily increase. However, the conventional electrical techniques applied at present give only spatially averaged properties [1–4]. Scanning probe technology, with its inherent two-dimensionality, offers unique capabilities for the measurement of electrical properties with high spatial resolution. To date, several techniques for the electrical * Corresponding author.

characterization of semiconductors have been developed. The most notable of these include scanning capacitance microscopy (SCM) [5], scanning resistance microscopy (SRM) [6], and Kelvin probe force microscopy (KFM) [7]. SCM has the ability to measure dopant profiles [5] in bulk-Si wafers and trapped charges in SiO2 or at SiO2 –Si interfaces [8,9] through the measurement of local capacitance changes. SRM has also been used to profile localized contact resistances on a semiconductor surface by monitoring the current at the probe tip when in contact with the surface, which gives an indirect measurement of electrically active dopant density [6]. KFM can be used to measure the surface distributions of electrical potential through detection of the electrostatic force between the tip and the surface [7]. These techniques are expected to be highly useful for the spatially resolved electrical characterization of SOI wafers. As yet however, there have been no reports regarding the application of these techniques to the characterization of thin SOI wafers. In this study, we used three types of scanning probe microscopes to visualize the depletion layer in SOI regions and the change in the thickness of the depletion layer according to the back bias voltage applied to the

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by implanted oxygen) wafers. We confirmed that positive fixed charges exist in the buried-oxide (BOX) layer, oriented parallel to the SOI layer. The spatial location of the positive charge was observed to differ between the two types of SOI wafers.

Fig. 1. Schematic of a beveled SOI wafer and measurement configuration.

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2. Experimental A basic atomic force microscope (AFM) and the KFM used in this work were parts of a commercially available system for observation in air [10]. The SCM measurements were made by attaching a high-sensitivity capacitance sensor to the AFM. The capacitance sensor was composed of an ultrahigh frequency (UHF) 1.2-GHz oscillator, a resonant circuit, and a frequency demodulator [11]. The measurement is based on the principle that the resonant frequency of the circuit changes according to the tip-sample capacitance, which is detectable by the frequency demodulator. Measurements of dC/dV under alternating current (ac) voltage were also recorded. SRM measurements were performed in constant current mode, in which the current between the probe tip and the wafer surface is maintained constant by applying a variable voltage to the sample, and a SRM image was constructed. These three measurements; SCM, SRM and KFM, were performed at different positions on the same sample. A Pt/Ticoated silicon tip was used for the force sensor. We used p-type SOI wafers fabricated by one of two processes, namely wafer bonding or wafer SIMOX. The thickness of the SOI layer was 200 nm, and the carrier concentration was constant for the two samples, introduced by ion implantation at a dose of 3.2× 1012 cm − 3 at 20 keV. The BOX thickness was 400 nm. Cross-sectioned SOI specimens were prepared by a standard polishing procedure, in which the specimen surface was beveled at 3° with reference to the (011) surface. After final polishing with a colloidal silica suspension, the SOI samples were heated at 300 °C under ultraviolet (UV) irradiation in order to both stabilize the surface through the growth of a thin oxide layer and reduce surface contamination [12]. A cross-section of an SOI specimen and the basic measurement configurations (except for KFM) are shown in Fig. 1. For SCM measurement, a variable ac voltage was applied to the top SOI layer via silver paste. A direct current (dc) bias voltage was applied independently to the Si substrate. For SRM measurement, a variable voltage was applied to the SOI wafer in order to maintain a constant current. The Si substrate was electrically grounded. For KFM measurement, the SOI layer and the Si substrate were electrically connected to the back contact.

3. Results and discussion Fig. 2. Topographic AFM image (a) and SCM images (b – f) of a cross-sectioned SIMOX wafer. Back bias voltages were applied to the Si substrate as follows: (a) 0, (b) +4, (c) + 8, (d) − 4, and (e) −8 V. Broken and solid lines indicate SOI/BOX and surface/SOI boundaries.

Fig. 2 shows AFM and SCM images obtained for the SIMOX wafer. In Fig. 2a, the broken and solid lines indicate the SOI/BOX and surface/SOI boundaries, respectively. The measured thickness (4 mm) of the SOI layer from the image is close to the 3.8 mm thickness

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Fig. 3. SRM images of: (a) SIMOX; and (b) bonded SOI wafers. Broken lines indicate SOI/BOX boundaries. (c and d) Cross-sectional profiles of SRM images corresponding to the SRM images shown in (a) and (b). Distances are measured from the SOI/BOX boundary.

estimated from the bevel angles. The slight discrepancy is attributed to inaccuracy in the bevel angle. Fig. 2b–f show SCM images obtained at back bias voltages of 0, + 4, + 8, − 4 and − 8 V, respectively. A 10 kHz ac voltage of 0.1 V was applied to the SOI layer. Here, it should be noted that the SCM image did not significantly change for the larger amplitude voltage of 2 V. In Fig. 2b, we can see the variation in dC/dV in the SOI layer. In addition to the BOX region, the SOI layer in the vicinity of the SOI– BOX interface is dark, whereas the SOI layer is intrinsically light. At positive back bias voltage, the darker region in the SOI layer extends across the SOI layer, as seen in Fig. 2c and d, extending further with increasing voltage. In contrast, the dark region receded under negative back bias voltage, as shown in Fig. 2e and f. At zero back bias voltage (Fig. 2b), the width of the dark region was 72 nm. However, at a back bias voltage of −8 V (Fig. 2f), the dark area has almost entirely disappeared. These results indicate that the carrier concentration in the vicinity of the SOI– BOX interface can be varied by applying a back bias voltage to the Si substrate. For the SOI layer with dopant density of 2×1017 cm − 3 used here, the depletion layer is estimated to be about 64 nm thick when a bias voltage of + 8 V is applied to the Si substrate through the 400-nm BOX layer. This is close to the 72-nm change in the dark region in the SOI layer observed between the back bias voltages of 0 and −8 V. This change in the thickness of the dark region

in the SOI layer is therefore considered to correspond to the increase in the thickness of the depletion layer. The depletion layer observed at a back bias voltage of 0 V is due to the fixed positive charges inherent in the BOX layer. Furthermore, it appears that the thickness of the depletion layer fluctuates depending on the location of the fixed charges. Although the data is not shown here, we obtained similar results for the bonded SOI wafer. This positive fixed charge in the BOX layer has also been reported previously based on spreading resistance profiles [13,14]. In order to verify the existence of the depletion layer at the SOI –BOX interface, we performed SRM measurements using the two types of SOI wafers. Fig. 3a and b show the SRM images obtained for a SIMOX and bonded SOI wafer, respectively. The SRM images were obtained at a constant current of 0.5 nA. The broken lines in Fig. 3a and b indicate the BOX/SOI boundary. The light regions represent areas of higher electric resistance. In Fig. 3a and b, the BOX layers have higher resistivity than the SOI layers. It should be noted that the region of higher resistance extends into the SOI layer in both types of SOI wafers. This means that there are regions of very low carrier concentration in the vicinity of the SOI–BOX interface owing to the existence of the depletion layer. Although the data is not seen here, the region with the higher resistivity extended to the surface side in the SOI layer by applying the positive back bias voltages. This result is consistent with the SCM results. The discrepancy in the thickness of the depletion layer observed by SCM and SRM is thought to be due to measurement at different positions or differences in the electrical information obtained. Fig. 3c and d show cross-sectional SRM profiles for the SIMOX and bonded wafers, respectively. The vertical and horizontal axes represent the distance from the SOI/BOX boundary and the contact resistance, respectively. In the SIMOX wafer, the resistance increases rapidly at the distance of about 0.5 mm from the SOI –BOX interface indicated by a broken line in Fig. 3c. In contrast, the resistance in the bonded SOI wafer increases gradually at a distance of 0.8 mm from the interface indicated by a broken line in Fig. 3d. These results suggest that the distribution of carrier concentration in the SOI layer differs between the SIMOX and the bonded SOI wafers. This is attributable to the dissimilarity in the fixed charge distributions in the BOX layer; however, this will need to be investigated in further detail. We then employed KFM to measure the potential distributions in the SOI wafers. Fig. 4a and b show the topographic and electric potential distribution images for the SIMOX wafer. In Fig. 4b, the bright line on the left corresponds to the BOX/Si-substrate boundary, and the bright line on the right corresponds to the

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Fig. 4. (a) Topographic; and (b) surface electric potential images for SIMOX wafer; (c) topographic; and (d) surface electric potential images for bonded SOI wafer. KFM measurements were performed at an ac bias voltage of 1 V at 8 kHz to induce the electrostatic force.

SOI – BOX interface. These bright lines represent areas of higher potential, in this case higher than the surrounding area by 189 mV. Fig. 4c and d show the topographic and potential distribution images for the bonded SOI wafer. Only one bright line can be seen in the potential image in this case, located 75 nm into the BOX layer from the Si substrate. The potential of the bright line is 116 mV higher than that of the surrounding area. The higher positive potential revealed in the KFM images indicates areas of higher positive charge concentration. Therefore, the bright lines represent accumulations of positive charge. In the case of the SIMOX wafer, the positive charge appears to accumulate at the edges of the BOX layer. In the bonded SOI wafer, the charge accumulates at a single point within the BOX layer. The difference in charge accumulation is considered to be due to the differences in the fabrication process, however the exact cause is a topic for further investigation.

4. Conclusion We employed scanning probe techniques to characterize cross-sectioned SOI wafers. We observed the thickening of the depletion layer in the SOI layer in the vicinity of the SOI –BOX interface by SCM under bias voltage applied to the Si substrate. SRM images showed that the electric resistance becomes higher in the SOI layer in the vicinity of SOI–BOX interface, and the change in resistance differed between the SIMOX and bonded SOI wafers. These results suggest that the fixed positive charges are inherently located in the BOX layer. KFM measurements identified the regions of positive charge concentration, which also differed between the SIMOX and bonded SOI wafers. In the present study, we have shown that the use of a combination of scanning probe techniques and operation modes represents a powerful tool for local electrical characterization of thin SOI

wafers. Further detailed analyses will be required in order to explain the experimental data consistently.

Acknowledgements This work was supported in part by the JSPS Research for the Future Program under the project ‘Ultimate Characterization Techniques of SOI wafer for the Nanoscale LSI Devices’.

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