Selectively grown vertical Si MOS transistor with reduced overlap capacitances

Selectively grown vertical Si MOS transistor with reduced overlap capacitances

Thin Solid Films 336 (1998) 306±308 Selectively grown vertical Si MOS transistor with reduced overlap capacitances D. Klaes a,*, J. Moers a, A. ToÈnn...

347KB Sizes 0 Downloads 12 Views

Thin Solid Films 336 (1998) 306±308

Selectively grown vertical Si MOS transistor with reduced overlap capacitances D. Klaes a,*, J. Moers a, A. ToÈnnesmann a, S. WickenhaÈuser a, L. Vescan a, M. Marso a, T. Grabolla b, M. Grimm a, H. LuÈth a a

Institut fuÈr Schicht-und Ionentechnik, Forschungszentrum JuÈlich GmbH, D-52425 JuÈlich, Germany b Institute for Semiconductor Physics, Walter-Korsing-Strasse 2, 15230 Frankfurt Oder, Germany

Abstract Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to de®ne the channel region. The vertical layout offers the advantages of achieving short channel lengths and high integration densities while still using optical lithography to de®ne lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for high speed applications. The use of SEG instead of blanket epitaxy avoids the deterioration of the Si± SiO2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First non-optimized p-channel MOSFETs with a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f T ˆ 2:3 GHz and f max ˆ 1:1 GHz. q 1998 Elsevier Science S.A. All rights reserved. Keywords: Low pressure chemical vapour deposition; Selective epitaxial growth; MOS transistor; Miller capacitance

1. Introduction Channel lengths are continually scaled to smaller dimensions to improve performance and packing density. CMOS technology with 1 Gbit feature sizes and beyond will use transistor gate lengths of 0.18 mm and smaller [1]. It seems to be questionable whether optical lithography can provide lines in these dimensions with small tolerances while ebeam and X-ray lithography still have to prove production maturity and cost effectiveness. A vertical transistor technology could solve the lithography problem for the gate layer. In addition vertical layouts permit higher integration densities due to the 3D stack. Within recent years different layouts of vertical MOSFETs using epitaxial layers to de®ne channel length have been proposed [2±4]. Vertical MOSFETs with channel lengths down to 40 nm have been fabricated. However, due to standard deposition techniques used for the polysilicon the gate does not only cover the channel region but also parts of source and drain. This leads to high parasitic gate/ source and gate/drain overlap capacitances (Miller capacitance) which limit high frequency applications of these devices. We therefore propose a novel vertical MOSFET layout (Fig. 1) where the polysilicon gate only covers the * Corresponding author.

channel region leading to considerably reduced overlap capacitances. 2. Device fabrication The processing starts with a SiO2±PolySi±SiO2 layer package which is performed by thermal oxidation, in situ doped polysilicon deposition and LPCVD-TEOS SiO2 deposition. Into this layer package holes are etched by anisotropic reactive ion etching to de®ne the active transistor area. After a standard RCA cleaning a PECVD gate oxide is deposited. An additionally deposited Si3N4 layer serves as a protection for this oxide. Then the lateral oxide and nitride are anisotropically etched using RIE and the vertical protection nitride is selectively removed with a wet-chemical etch step in H3PO4. The following selective epitaxial p 1/n/p 1-growth is carried out in a cold-wall low pressure chemical vapour deposition (LPCVD) system at 0.12 Torr at 8008C, using SiCl2H2 as source gas and PH3 and B2H6 as doping gases. During epitaxy, facets, which are slower growing crystallographic plains with different surface potentials, occur at the oxide interface (Fig. 2). The facet growth is a function of growth temperature, Cl/H ratio and supersaturation and depends on the SiO2 side wall orientation [5,6]. On our growth conditions k111l and k311l facets appear for SiO2-

0040-6090/98/$ - see front matter q 1998 Elsevier Science S.A. All rights reserved. PII S0040-609 0(98)01248-6

D. Klaes et al. / Thin Solid Films 336 (1998) 306±308

307

Fig. 1. Sketch of the vertical MOSFET.

side walls parallel to k110l. As a consequence the channel length is shorter than the distance between the two p±n junctions in the volume area, leading to a shift of punchthrough to higher voltages [7]. After epitaxy the upper oxide and the polysilicon outside the transistor structure are removed by RIE etching. The polysilicon is insulated by a PECVD SiO2 spacer. Finally, the contact holes are etched, a NiSi salicide process is performed and an aluminium metallization is evaporated. 3. Device characteristics Typical subthreshold characteristics of the fabricated selectively grown transistors are shown in Fig. 3. The threshold voltage is V TH ˆ 22:8 V due to the thick gate oxide (12 nm) and the n-doped polysilicon gate. A reduction down to 21.7 V should be possible by exchanging the ndoped polysilicon gate by a p-doped one. In the sub-threshold region the slope is 160 mV/dec at V D ˆ 21 V. Improvements will be expected by doping optimization. A good leakage performance is demonstrated, providing a good switching behaviour. The output characteristics are shown in Fig. 4. The transistors scale well with the gate width de®ned by optical lithography in the range of 4±160 mm. For a gate oxide thickness of 12 nm a transconductance of 90 mS/mm at V G ˆ 24 V and V D ˆ 23 V has been obtained which is a high value for a p-channel MOSFET with oxide thickness

Fig. 2. SEM cross section of epitaxially grown transistor structure.

Fig. 3. Subthreshold characteristics of the vertical MOSFET.

.10 nm. Typical short channel behaviour can be seen. Punch-through starts for drain voltages of 23.5 V (V G ˆ 22 V). The drain-induced-barrier-lowering (DIBL) is 300 mV/V. Current gain (h21) and unilateral power gain (GU) as a function of the frequency have been calculated from an Sparameter analysis (Fig. 5). The extracted cut-off frequencies are f T ˆ 2:3 GHz and f max ˆ 1:1 GHz for the 130-nm p-MOSFET.

4. Conclusions Vertical p-MOS transistors with channel lengths down to 130 nm have been fabricated using selective epitaxial growth by LPCVD to de®ne the channel region. Although a 12-nm PECVD gate oxide was used the transistors show a high transconductance and a low off current (10 211 A/mm). Due to self aligned facet growth the channel length and the volume diode thickness which normally limits the parasitic bipolar transistor of the blanket grown devices can be designed more independently. As the epitaxy is performed

Fig. 4. Drain characteristics of the vertical MOSFET.

308

D. Klaes et al. / Thin Solid Films 336 (1998) 306±308

GHz for a 130-nm p-MOSFET with 12-nm thick gate oxide indicate the potential of vertical MOSFETs for future CMOS applications.

References

Fig. 5. Extracted h21 and GU.

after gate oxide deposition the use of a strained SiGe channel is possible for RF optimization. The cut-off frequencies f T ˆ 2:3 GHz and f max ˆ 1:1

[1] N.N. SIA, Process of the Future, Roadmap of the SIA, Solid-State Technol. (1995) 42. [2] D. Behammer, L. Vescan, R. Loo, J. Moers, A. MuÈck, H. LuÈth, T. Grabolla, Electron. Lett. 32 (1996) 406. [3] L. Risch, Th. Aeugle, W. RoÈsner, Proc. ESSDERC 97, Stuttgart, pp. 34±41. [4] H. Gossner, I. Eisele, L. Risch, Jpn. J. Appl. Phys. 33 (4) (1994) 2423. [5] L. Vescan, in: K. Eberl (Ed.), Low Dimensional Structures Prepared by Epitaxial Growth or Regrowth on Patterned Substrates, Kluwer, Dordrecht, 1995 pp. 173±184. [6] L. Vescan, C. Dieker, A. Hartmann, A. van der Hart, Semicond. Sci. Technol. 9 (1994) 387. [7] R. Loo, L. Vescan, D. Behammer, J. Moers, et al., Thin Solid Films 294 (1997) 267.