GaN heterostructure field effect transistors with junction field plates

GaN heterostructure field effect transistors with junction field plates

Superlattices and Microstructures xxx (xxxx) xxx–xxx Contents lists available at ScienceDirect Superlattices and Microstructures journal homepage: w...

3MB Sizes 0 Downloads 27 Views

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Contents lists available at ScienceDirect

Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices

Simulation design of high Baliga's figure of merit normally-off PeGaN gate AlGaN/GaN heterostructure field effect transistors with junction field plates Zhiyuan Bai, Jiangfeng Du∗, Hao Wang, Xiaoyun Li, Qi Yu State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, PR China

A R T IC LE I N F O

ABS TRA CT

Keywords: PeGaN gate AlGaN/GaN heterostructure field effect transistors Normally-off Junction field plate Baliga's figure of merit Breakdown voltage

In this paper, we conducted a numerical analysis on novel Normally-off PeGaN gate AlGaN/GaN heterostructure field effect transistors with junction field plates (JFP-HFET). The breakdown voltage (BV) was significantly improved with the introduction of the junction field plate (JFP), which can make a rectangular distribution of the electric field in the GaN channel between the gate and the drain. The highest BV of 1340 V of JFP-HFET could be achieved with the gate to the drain distance Lgd = 6 μm, the length of the P-type region of the JFP Lp = 5.8 μm, the thickness of the JFP Tj = 500 nm, the doping concentration of P-type region of the JFP Np = 1 × 1017 cm−3, and the Al fraction of the AlGaN JFP xAl = 0.25. The optimum parameters of the JFP-HFET were achieved by considering both the principle of charge balance and the practical fabrication of the III-V devices. The highest Baliga's figure of merit (BFOM) 1.2 GW/cm2 was obtained under the conditions of Lgd = 6 μm, Lp = 5.8 μm, Tj = 100 nm, Np = 6 × 1017 cm−3, and xAl = 0.3. CeV, turn-on and turn-off processes revealed that the JFP-HFET showed better switching characteristics than that of the HFET with metal field plate.

1. Introduction Gallium nitride (GaN) semiconductor devices have gained considerable attention and broad prospects in high voltage application in recent years because of the high breakdown field of GaN and successful progresses in growth of III-V heterostructure on silicon [1–3]. AlGaN/GaN heterostrurcture field effect transistors (HFETs) with high breakdown voltage (BV), low on-resistance thus high Baliga figure of merit (BFOM) are extensively studied and have become one of major interests in the field of the power electronics [4,5]. However, these devices often show normally-on behavior due to the natural 2 dimensional electron gas (2DEG) which is induced by polarization effects of III-V heterojunction. This behavior of AlGaN/GaN HFETs would hinder the design of gate-control circuit, thus exclude them from most power electronics applications. AlGaN/GaN HFETs with a p-type gate have been reported by many literature. By using a p-type GaN or AlGaN layer under the gate metal, the threshold voltage of HFETs can reach around 1.5 V and can realize normally-off operation with simple and controllable fabrication processes [6–10]. The results show that p-GaN gate AlGaN/GaN HFETs are promising for GaN based power electronics commercialization [11]. However, an electric field (E-field) peak exists at the corner of the gate of lateral kinds of semiconductor devices such as LDMOSFETs [12] and AlGaN/GaN HEMTs [13,14], thus cause a premature breakdown of these kinds



Corresponding author. E-mail address: [email protected] (J. Du).

https://doi.org/10.1016/j.spmi.2018.09.005 Received 12 June 2018; Received in revised form 3 September 2018; Accepted 5 September 2018 0749-6036/ © 2018 Elsevier Ltd. All rights reserved.

Please cite this article as: Bai, Z., Superlattices and Microstructures, https://doi.org/10.1016/j.spmi.2018.09.005

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 1. Schematic structure of the simulated (a) conventional PeGaN gate HFETs, (b) MFP-HFETs and (c) proposed JFP-HFETs.

of semiconductor devices. As one of these kinds of lateral semiconductor device, p-GaN AlGaN/GaN HFETs also suffered from this problem [15]. Although metal field plates (MFP) can modulate the E-field distribution in the channel layer, a new E-field peak is induced at the end MFP, thus hinder the further improvement of the BV [14,16]. So the BFOM of p-GaN gate AlGaN/GaN HFETs is still far from the material limits of GaN. Junction field plates (JFP) have been reported as a new method to improve the BV and BFOM of lateral diffusion metal-oxide-semiconductor field effect transistors (LDMOSFETs). Compared to the MFP LDMOSFETs, the JFP LDMOSFETs achieves a superior trade-off between RON, sp and BV [12]. In this study, a junction field plate AlGaN/GaN HFETs (JFP-HFETs) was proposed to improve the BV of the p-GaN gate devices, because the p-GaN gate GaN HFET have well experimentally studied and have shown great application prospects in power electronics. In the present study, the BV of the AlGaN/GaN HFETs can be significantly enhanced by adding a JFP on the AlGaN barrier between the gate and the drain. The forward characteristics of JFP-HFETs only showed a small degradation when compared to the conventional HFETs. So the proposed JFP-HFETs can achieve a high BFOM. CeV simulation was also conducted to determine whether JFP-HFETs had a better switching characteristics than MFP PeGaN gate HFET. 2. Device structure, fabrication and models The device structure of the conventional PeGaN gate HFETs, MFP-HFETs and proposed JFP-HFETs is shown in Fig. 1. The epitaxial structure of the device consisted of a 2.6 μm thick GaN buffer layer, a 300 nm GaN channel layer, and a 12.5 nm AlGaN barrier layer with a 25% Al content. An 80 nm PeGaN under the gate metal is grown on the AlGaN barrier to realize normally-off operation. The hole density of the PeGaN is set as 1 × 1018cm−3. A Si3N4 passivation layer with a thickness of 500 nm was added to the AlGaN barrier layer. The source length (LC), drain length (LD), gate length (LG), gate-to-source distance (LGS) and gate-to-drain distance (LGD) of the device were 1, 1, 0.8, 0.75, and 6 μm, respectively. All of the parameters used in the simulation were based on the experimental results of Ref. [10]. And were listed in Table 1. High resistive GaN buffer layer can be realized by doping C during the growth of the GaN buffer [17].In the Ref.17, the authors have reported traps energy level of C doped buffer. For low C doping concentration (NA = 1 × 1016cm−3), there is only one energy level of the C related acceptor-like traps which is 0.59 eV under the conduction band. So here high resistance of GaN buffer layer were simulated as acceptor traps doped GaN with an energy level of EC0.59 eV and a density of 1 × 1016 cm−3. In the MFP-HFET in Fig. 1 (b), the gate MFP and the source MFP placed on the passivation layer with a distance to the surface of AlGaN barrier layer were 200 nm and 500 nm, respectively, and both kinds of MFPs are typical in the GaN based high voltage devices [4,18]. In the JFP-HFET in Fig. 1 (c), the JFP consisted of a P-type AlGaN layer and an N+-type 2

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Table 1 Simulated device specifications. Parameters

Values

Parameter captions

LG LGS LGD LS LD Tbarr Tch Tbuff TGaN NpGaN NA EA LGFP LSFP dGFP dSFP xAl Nn Tj LP NP

0.8 μm 0.75 μm 6 μm 1 μm 1 μm 12.5 nm 300 nm 2.6 μm 80 nm 1 × 1018cm−3 1 × 1016cm−3 0.59 eV 1 μm 2 μm 200 nm 500 nm 0.3–0.05 1 × 1020cm−3 50–500 nm 0.6–5.8 μm 5–200 × 1016cm−3

Gate length Distance from gate to source Distance from gate to drain Source length Drain length Thickness of Al0.25Ga0.75N barrier layer Thickness of GaN channel layer Thickness of GaN buffer layer Thickness of PeGaN Density of hole in the PeGaN Density of acceptor-like traps in GaN buffer Energy level of acceptor-like traps Length of the gate MFP Length of the source MFP Distance from the gate MFP to the AlGaN Distance from the source MFP to the AlGaN Al composition of the JFP Density of electron in the N+eAlGaN Thickness of JFP Length of the PeAlGaN Density of hole in the PeAlGaN

AlGaN layer, which formed a PN+ junction between the gate and the drain. There were two reasons that p-AlGaN/n-AlGaN was used for the JFP rather than p-GaN/n-GaN. On the one hand, the critical electric field of AlGaN is much higher than that of GaN (3.4 MV/ cm) [19]. On the other hand, the GaN cap layer can strongly affect the on-state resistance of the HFET [20]. The traps and/or charges at the SiNx/AlGaN interface were not taken into consideration during the simulation of both DC and dynamic characteristics of GaN HFET. Although these traps and charges have an impact on the switching behavior, the three kinds of devices were compared under the same conditions which the SiNx/AlGaN interface traps were not included. The fabrication process of the JFP-HFET can be more complex than the MFP-HFET. After growth of the PeGaN/AlGaN/GaN heterostructure by metal organic chemical vapor deposition (MOCVD) [1], the process can be started with forming mesa isolation by using BCl3/Cl2 in inductive coupled plasma reactive ion etching (ICP-RIE). Surface treatment can be conducted after select etching the PeGaN layer [15]. Then a patterned dielectric (Si3N4 or SiO2) is used as the regrowth mask to perform selective area regrowth of PeAlGaN. Selective Si-implanted can be conducted by using a thick photoresist (PR) layer as the mask layer to form an N+eAlGaN region. The steps of metal contacts formation are similar to that in Ref. [4]. So the formation of JFP needs regrowth process and selective Si-implanted process, and the formation of MFP only needs growth of metal on the dielectric. TCAD simulations were conducted by using Silvaco ATLAS. The models used in the simulation included the Shockley–Read–Hall (SRH) model, the polarization model and the Selberherr's impact ionization model, and these models were discussed in our previous works [21–23]. The Self-heating effect was not considered during the simulation. All calculations were based on the Fermi–Dirac statistics. The source and drain was defined as an Ohmic contact, whereas the gate was defined as a Schottky contact with a work function of 4.1 eV [24]. The reason of the improvement of JFP on BV is illustrated in Fig. 2. When VDS and VGS was zero, as shown in Fig. 2 (a), the depletion region of 2DEG was under the gate. When VDS further increased, as shown in Fig. 2 (b) and Fig. 2 (c), the depletion region of Source connected contact

Source connected contact N+-AlGaN

P-AlGaN

G

-

-

-

Pr Pr Pr

-

-

+

+

-

+

A h A h A h A Pr

-

-

Pr Pr

-

-

Pr Pr Pr Pr

A- h+ A- h+ A- h+ AA- h+ A- h+ A- h+ A-

-

-

Pr

AA-

-

A

Depletion region AlGaN barrier

D

-

Pr

e-

e-

e-

e-

e-

e-

e-

-

-

-

Pr Pr Pr Pr

A - h+ A A - h+ A -

A-

A-

A-

A-

A-

A-

-

-

-

+

A h A-

Pr Pr

-

Pr Pr Pr

-

-

-

A

A

A

Pr

D

e-

e-

e-

e-

e-

e-

Pr

-

-

Pr Pr

-

-

-

-

Pr Pr Pr Pr- Pr-

A-

A-

A-

A-

A-

A-

A-

A-

A-

A-

A-

-

-

A-

-

A

A

-

Pr

D

Depletion region AlGaN barrier

e-

Depletion region GaN channel

(b) VDS medium bias

(a) VDS zero bias

-

-

Pr Pr Pr

A

Pr

e-

-

P-GaN

-

e-

N+-AlGaN

P-AlGaN

G

-

+ + + + + + + + + Pr+ Pr Pr Pr Pr+ Pr Pr Pr Pr Pr Pr Pr+

e-

GaN channel



-

Depletion region AlGaN barrier

+ + + + + + + + + Pr+ Pr Pr Pr Pr+ Pr Pr Pr Pr Pr Pr Pr+

e-

-

Dielectric VGS = 0 V

-

P-GaN

-

Source connected contact N+-AlGaN

P-AlGaN

G

-

-

Pr

Dielectric VGS = 0 V

+ + + + + + + + + Pr+ Pr Pr Pr Pr+ Pr Pr Pr Pr Pr Pr Pr+

e-

e-

e-

e-

e-

e-

e-

e-

e-

Depletion region GaN channel

(c)VDS complete depletion bias

Fig. 2. Proposed JFP model, e : Free electron; h : Free hole; Pr : Positive polarization charge; Pr−: Negative polarization charge; A+: Ionized donor acceptor. +

+

3

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 3. The DC characteristics of conventional PeGaN gate HFETs, MFP-HFETs, proposed JFP-HFETs and optimized JFP-HFETs (a) Output curves (b) Semilog plot and linear plot of the transfer curves.

PeAlGaN of JFP started to extend to the gate side, due to the PN+ junction was negative bias. The electron in the 2DEG channel could be depleted by the ionized acceptor in the PeAlGaN, thus the E-field along the y-direction of PeAlGaN could modulate the E-field along the 2DEG channel through the depletion and charge compensation effects between the JFP and the 2DEG channel, which was similar to superjunction [25]. The almost linear E-field distribution which came from the depleted PeAlGaN in the JFP can modulate the E-field along the 2DEG channel for JFP-HFET, thus the E-field along the 2DEG channel was more uniform and the average E-field strength could become much higher than the devices with MFPs.

3. Results and discussion 3.1. Device characteristics of JFP-HFETs The DC characteristics of conventional PeGaN gate HFETs, MFP-HFETs and proposed JFP-HFETs are shown in Fig. 3. The thickness of JFP Tj, the length LP, the Al fraction xAl and hole concentration NP of the PeAlGaN were 500 nm, 5.8 μm, 0.25 and 1 × 1017 cm−3, respectively. These parameters were randomly defined to obtain the change of IeV characteristics when the JFP was induced in the PeGaN gate HFET and would be optimized in the next section. All the DC characteristics of the conventional PeGaN gate HFET were similar to the experimental results of the Ref. [10]. As illustrated in Fig. 3, the DC characteristics of the PeGaN gate HFETs and MFP-HFETs were the same, which indicated that MFP should not influence the forward characteristics of the device. The on-state resistance Ron changed from 10.2 Ω mm to 12.5 Ω mm when the JFP was placed on the AlGaN barrier. The maximum drain current Idsmax of JFP-HFET and PeGaN gate HFETs at VDS = 10 V and VGS = 7 V were 225 mA/mm and 235 mA/mm, respectively. As illustrated in Fig. 3 (b), the threshold voltage Vth and on/off ratio kept 1.6 V and 109, respectively. This indicated that JFP should not strongly influence the forward characteristics of the AlGaN/GaN HFET when the NP was 1 × 1017 cm−3, Tj was 500 nm and LP was 5.8 μm. The increase in NP, Tj and LP may cause further depletion of the 2DEG channel under the P-type AlGaN layer, thus make the forward characteristics even worse than it in Fig. 3. So these parameters need further optimization. The optimization the NP, Tj and LP was conducted by considering the fabrication capability, the charge balance between the PeAlGaN and the 2DEG channel, and the maximization of BFOM. The optimum NP, Tj and LP were 6 × 1017 cm−3, 100 nm and 5.8 μm, respectively, under the xAl of 0.3, and IeV characteristics of the optimized JFP-HFET was also shown in Fig. 3. The Ron and the Idmax of the optimized JFP-HFET was 14.3 Ω mm and 216 mA/mm, respectively. The breakdown characteristics of conventional PeGaN gate HFETs and proposed JFP-HFETs are shown in Fig. 4 (a).The thickness of JFP Tj, the length LP of and hole concentration NP of the PeAlGaN were 500 nm, 5.8 μm and 1 × 1017 cm−3, respectively. The BV of conventional PeGaN gate HFETs with Lgs = 0.75 μm, Lg = 0.8 μm, Lgd = 6 μm was 600 V and was same to the experimental results in Ref. [10], while that of JFP-HFET was 1340 V. It is obvious that JFP can significantly improve the BV of AlGaN/GaN HFET. This improvement can be explained by the E-field distribution along the 2DEG channel in Fig. 4 (b). When JFP was placed on the surface of AlGaN barrier, the distribution of the E-field was more uniform than that of conventional HFET, owing to the assisted-depletion effect of the JFP on the 2DEG channel. On the other hand, the charge between the junction interface should be balanced when the device operated in reverse blocking state. So the hole can be removed by the source and the negative ionized acceptor can prompt the depletion of the 2DEG channel. Fig. 5 is the comparison of the potential distribution of the conventional p-GaN gate HFET, MFP-HFET and the proposed JFPHFET at breakdown state. For the p-GaN gate HFETs in Fig. 5 (a), the drift region cannot be fully depleted and all potential contours were collected at the gate edge, wherein the E-field concentrated thus premature breakdown happened. As shown in Fig. 5 (b), The MFP made the distribution of the potential line more uniform along the channel than that in the p-GaN gate HFETs without MFPs. However, most of the potential contours were collected at the edge of MFP, resulting in an E-field peak at the edge of the MFP. Thus, the average E-field strength of MFP-HFETs was far smaller than the limit of GaN material. As shown in Fig. 5 (c), the electric potential 4

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 4. (a) The BV curves and (b) the E-field distribution along the channel of conventional PeGaN gate HFETs, MFP-HFETs, and proposed JFPHFETs.

Fig. 5. The potential distribution (a) conventional PeGaN gate HFETs, (b) MFP PeGaN gate HFETs and (c) proposed JFP-HFETs.

between gate and drain was uniformly distributed. So the shape of the E-field distribution was similar to a rectangle. Then, the average E-field strength was obviously increased. So the JFP-HFET had the highest breakdown voltage in all three kinds of HFETs. 3.2. The optimization of JFP-HFETs Fig. 6 shows the optimization results of the length of the P-type JFP region Lp. The thickness of JFP Tj, the hole concentration NP and the Al content xAl of the PeAlGaN were 500 nm, 1 × 1017 cm−3 and 0.25, respectively. Both BV and Ron increased with the increase in the Lp, thus caused an increase in the BFOM. When the Lp increased from 2.3 to 5.8 μm, the BV and Ron increased from 795 V to 11 Ω mm to 1340 V and 12.5 Ω mm, respectively. The BFOM increased as the same trend as the increase in the BV, and the highest BFOM of 1.37 GW/cm2 could be achieved when the Lp was set as 5.8 μm. When LP exceeded 4.8 μm, the increase in BV was gradual. The increase in the Ron can be explained as the partly depletion of the 2DEG channel when a P-type AlGaN layer is placed on the barrier layer. The increase in the BV can be explained by the distribution of the E-field in the GaN channel layer. As is shown in Fig. 6 (b), the E-field distribution was extracted at y = 13 nm in the GaN channel layer. When the P-type AlGaN layer of the JFP extended, the distribution of the E-field becomes uniform, and the E-field peaks at both gate side and drain side were reduced. As discussed above, the optimum Lp was achieved as a result of 4.8–5.8 μm. 5

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 6. The optimization of the Lp (a) the Lp dependence of the BV and BFOM (b) the E-field distribution at y = 13 nm of JFP-HFETs with different Lp.

The optimization of Np and Tj is shown in Fig. 7. The Lp and xAl were set as 5.8 μm and 0.25, respectively. According to charge balance between the P region in the JFP and electron concentration Ns in the 2DEG channel, the approximate RESURF criterion Np and Tj can be given by Ref. [12], Np•Tj = Ns

(1) −2

The 2DEG density was ∼5 × 10 cm which was calculated by the polarization model. As illustrated in Fig. 7 (a), the BV increased with the increase in the Np firstly, when Np•Tj reached 5 × 1012 cm−2, the BV started to decrease with the increase in the Np. The Ron of JFP-HFETs with different Tj kept nearly the same, but raised rapidly when the Np was over 5 × 1017 cm−3. Fig. 7 (b) shows the E-field distribution at the AlGaN/GaN interface (y = 13 nm) of each Np•Tj cases. When Np•Tj was 5 × 1012 cm−2, the rectangular distribution of the E-field was more uniform than other two cases, thus the BV of the devices with Np•Tj = 5 × 1012 cm−2 reached 1340 V, and was the highest in all three cases. When Np•Tj was less than 5 × 1012 cm−2, such as 5 × 1011 cm−2, the BV can still reach 780 V, which was higher than the BV of conventional PeGaN gate HFET. But there was an E-field peak at the gate-side JFP edge which reached the limits of the GaN material, and the distribution of the E-field resembled a triangle. So the BV can be further improved by increasing Np•Tj in this case. When Np•Tj was above 5 × 1012 cm−2, such as 3 × 1013 cm−2 in Fig. 7 (b), the BV was only 220 V, which was less than the BV of conventional PeGaN gate HFET. There was an E-field peak at the drain-side JFP edge which reached the limits of the GaN material, and the distribution of the E-field resembled a triangle. The breakdown of the device happened at the drain-side JFP edge, and the BV can only be improved unless decreasing Np•Tj in this case. The optimization results in Fig. 7 (a) indicated that the optimum Np and Tj were 1 × 1017 cm−3 and 500 nm, respectively. However, an (Al)GaN cap layer over the barrier layer was usually as thick as ∼100 nm in experimental results [6–10]. So here we chose Np = 5 × 1017 cm−3 and Tj = 100 nm as the optimum structure parameters. The optimization of Al fraction xAl of the AlGaN JFP is shown in Fig. 8. Fig. 8 (a) shows the relationship between BV/Ron and Np at different xAl. As discussed above, Tj and Lp were set as 100 nm and 5.8 μm, respectively. It was obvious that the optimum Np•Tj was not the same for different xAl, and the optimum Np•Tj was increased with the increase in xAl. When xAl increased from 0.15 to 0.3, the electron density in the 2DEG channel was increased from ∼1 × 1012 cm−2to 6 × 1012 cm−2, thus caused an increase in the optimum Np•Tj. On the other hand, the increase in the electron density in the 2DEG channel induced a decrease in the Ron. So the Ron of JFPHFETs with high xAl was lower than that of JFP-HFETs with low xAl. The BV of JFP-HFETs with each optimum Np•Tj was 1290 V. So 12

Fig. 7. The optimization of the Tj and Np (a) the Tj and Np dependence of the BV and Ron (b) the electric field distribution at y = 13 nm of JFPHFETs with different Np•Tj. 6

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 8. The optimization of the Al fraction xAl of the AlGaN JFP(a) the xAl and Np dependence of the BV and Ron (b) the optimizaiton of Np at xAl = 0.3.

JFP-HFETs with the highest xAl of 0.3 showed the highest BFOM when Np•Tj∼6 × 1012 cm−2. The BFOM of JFP-HFETs with xAl of 0.3 was shown in Fig. 7(b). The highest BFOM was 1.2 GW/cm2. Above all, the optimum structure parameters of the JFP-HFET can be achieved by considering both RESURF theory and the practical experimental limits. The highest BFOM of 1.2 GW/cm2 can be achieved with a xAl of 0.3, a Tj of 100 nm, a Lp of 5.8 μm and a Np of 6 × 1017 cm−3.

3.3. Benchmarking of BV versus Ron.sp In Fig. 9, the benchmark plot of BV versus Ron,sp for PeGaN gate HFETs is shown. C-doped or AlGaN buffer [6,30], lattice matched substrate [31,32], and other method [10,15,20,29] such as high-resistivity GaN Cap Layer [15] have been used to improve the reverse characteristics of PeGaN gate HFETs, thus achieve a high BFOM. A BV of 2800 V was achieved with a Lgd = 20 μm by using bulk GaN substrate, which demonstrated a BFOM of 5.9 GW/cm2 [31]. X. Li et al. reported a 200 mm GaN-on-SOI PeGaN gate HFETs

Fig. 9. The benchmark plot of BV versus Ron,sp for PeGaN gate GaN HFET. 7

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 10. Simulated C–V Characteristics results of conventional PeGaN gate HFETs, MFP PeGaN gate HFETs and JFP-HFETs (a) Ciss (b) Coss (c) Crss.

for monolithic integration, this kind of device showed a BV of 600 V, yielding a BFOM of 423 MW/cm2, and all the simulated static characteristics of the conventional PeGaN gate HFET in this paper were compared to this experimental result [10]. In this work, the optimum JFP-HFET had a BFOM as high as 1.2 GW/cm2 with a BV of 1290 V, which was much higher than results in Ref.10. 3.4. Switching characteristics CeV characteristics were simulated in Fig. 10. This simulation method was based on the modeling of the Si vertical MOSFET [26]. The three inter-electrode capacitances Cgs, Cgd, and Cds were simulated, respectively, and then converted into the input capacitance Ciss, the output capacitance Coss, and the reverse capacitance Crss by Ref. [27]. Ciss = Cgs + Cgd, Coss = Cgd + Cds, Crss = Cgd

(2)

The HFETs were considered switching between 0 and 200 V [10], so here the highest value of the VDS was set as 200 V. All CeV simulations were conducted under VGS = 0 V and simulation frequency fs = 1 MHz. The gate width Wg of all three devices was the same as Ref. [10] and was set as 36 mm. Some of the definitions of the switching parameters were based on the datasheet of the GaN based power switching devices [28]. As shown in Fig. 10 (a), the Ciss of the conventional PeGaN gate HFET, the MFP-HFET and the JFP-HFET were 4.2 pF, 25.3 pF and 9.2 pF, respectively at VGS = 0 V and VDS = 200 V. Compared to that of the MFP-HFET, the Ciss of JFP-HFETs was much lower, leading to substantially lower Qg than that of MFP-HFET. On the other hand, compared to that of the conventional PeGaN gate HFET, the Ciss of JFP-HFETs was higher due to an increased Cgs induced by the source-connected contact of the JFP. On the other hand, JFP-HFET showed a similar Crss and Coss to that of MFP-HFET at VGS = 0 V and VDS = 200 V. The Coss the conventional PeGaN gate HFET, MFP-HFET and JFP-HFET were 1.1 pF, 2.8 pF and 2 pF, respectively. The output charge Qoss can be calculated by the integration of the Coss from 0 to 200 V, and the Qoss of the three devices were 0.2 nC, 1.7 nC and 1.2 nC, respectively. The Qoss of the JFP-HFET was one order of magnitude higher than that of the conventional PeGaN HFET due to the junction capacitance between the source and the drain which led to an increase in Cds. The Crss of the conventional PeGaN gate HFET, MFPHFET and JFP-HFET were 0.9 pF, 0.4 pF and 0.4 pF, respectively at VGS = 0 V and VDS = 200 V. Both MFP and JFP devices showed a smaller Crss than that of the conventional PeGaN gate HFET, because the depletion region between the gate and the drain was extended by the MFP or the JFP at VDS = 200 V, thus led to a small Cgd. The turn-on and turn-off processes of HFETs with JFP and MFP are shown in Fig. 11 with the gate width Wg of 36 mm. Test circuit 8

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

Fig. 11. Simulated Switching Characteristics results of MFP-HFETs and JFP-HFETs (a) the turn-on process of MFP-HFETs (b) the turn-on process of JFP-HFETs (c) the turn-off process of MFP-HFETs (d) the turn-off process of JFP-HFETs.

used in the simulation was the same as that in Ref. [33]. The dc voltage at the drain side VDC was set as 200 V, while the gate charging resistor Rg was set as 5 Ω, the gate current pulse with 1 A had a period of 3 μs and a width of 1 μs. For comparison of switching characteristics of both devices, the rising and falling edges of the pulse were defined as zero time. The turn-on processes of MFP-HFET and JFP-HFET were illustrated in Fig. 11 (a) and Fig. 11 (b), the turn-on time ton was defined by the time between 10% of the highest VGS to 10% of the highest VDS [28]. The ton of MFP-HFET was 8.3 ns while that of JFP-HFET was 6.4 ns. Otherwise, Qg of MFP-HFET and JFP-HFET were 6.7 nC and 9.1 nC respectively. The turn-off processes of MFP-HFET and JFP-HFET were illustrated in Fig. 11 (c) and Fig. 11 (d), the turn-off time toff was defined by the time between 90% of the highest VGS to 90% of the highest VDS [28]. The toff of MFP-HFET was10.8 ns while that of JFP-HFET was 11.3 ns. So the JFP-HFET showed better switching characteristics than MFPHFET. 4. Conclusion A numerical analysis on JFP-HFET was conducted. The breakdown voltage (BV) was significantly improved from 800 V to 1340 V with Lgd = 6 μm, Lp = 5.8 μm and Tj = 500 nm when a JFP was placed onto the AlGaN barrier between the gate and the drain. The optimum parameters of the JFP-HFET were achieved by considering both the principle of charge balance and the practical fabrication of the III-V devices. The highest Baliga's figure of merit (BFOM) 1.2 GW/cm2 was obtained under the conditions of Lgd = 6 μm, Lp = 5.8 μm, Tj = 100 nm, Np = 6 × 1017 cm−3, and xAl = 0.3. CeV and switching simulation revealed that the JFP-HFET had better switching characteristics than that of the HFET with MFP, but a larger energy loss than the conventional PeGaN gate HFET in power switching applications. Improvements such as tri-gate like JFP structure [5] should be made to solve this problem in our future works. Acknowledgments This work was financially supported by the National Natural Science Foundation of China under Project No. 61376078. References [1] K.J. Chen, O. Häberlen, A. Lidow, C. l Tsai, T. Ueda, Y. Uemoto, Y. Wu, GaN-on-Si power technology: devices and applications, IEEE Trans. Electron. Dev. 64 (3) (Mar. 2017) 779–795, https://doi.org/10.1109/ted.2017.2657579. [2] Y. Zhang, K.H. Teo, T. Palacios, Beyond thermal management: incorporating p-diamond back-barriers and cap layers into AlGaN/GaN HEMTs, IEEE Trans. Electron. Dev. 63 (6) (June 2016) 2340–2345, https://doi.org/10.1109/TED.2016.2553136. [3] B.J. Baliga, Gallium nitride devices for power electronic applications, Semicond. Sci. Technol. 28 (7) (Jul. 2013), https://doi.org/10.1088/0268-1242/28/7/

9

Superlattices and Microstructures xxx (xxxx) xxx–xxx

Z. Bai et al.

074011 074011–1–074011-8. [4] R. Chu, A. Corrion, M. Chen, R. Li, D. Wong, D. Zehnder, B. Hughes, K. Boutros, 1200-V normally-off GaN-on-Si field-effect transistors with low dynamic onresistance, IEEE Electron. Device Lett. 32 (5) (May 2011) 632–634, https://doi.org/10.1109/LED.2011.2118190. [5] Jun Ma, Elison Matioli, High performance tri-gate GaN power MOSHEMTs on silicon substrate, IEEE Electron. Device Lett. 38 (3) (Mar. 2017) 367–370, https:// doi.org/10.1109/LED.2017.2661755. [6] O. Hilt, F. Brunner, E. Cho, A. Knauer, E. Bahat-Treidel, J. Würfl, Normally-off high-voltage p-GaN gate GaN HFET with carbon-doped buffer, Proc. Int. Symp. Power Semicond, May 2011, pp. 239–242, , https://doi.org/10.1109/ISPSD.2011.5890835. [7] I. Rossetto, M. Meneghini, O. Hilt, E.B. Treidel, C.D. Santi, S. Dalcanale, J. Wuerfl, E. Zanoni, G. Meneghesso, Time-dependent failure of GaN-on-Si power HEMTs with p-GaN gate, IEEE Trans. Electron. Dev. 63 (6) (Apr. 2016) 2334–2339, https://doi.org/10.1109/TED.2016.2553721. [8] M. Tapajna, O. Hilt, E. Bahat-Treidel, J. Würfl, J. Kuzmík, Investigation of gate-diode degradation in normally-off p-GaN/AlGaN/GaN highelectron-mobility transistors, Appl. Phys. Lett. 107 (19) (Oct. 2015) 193506, https://doi.org/10.1063/1.4935223. [9] Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, D. Ueda, Senior Member, IEEE, “Gate injection transistor (GIT)—a normally-off AlGaN/GaN power transistor using conductivity modulation, IEEE Trans. Electron. Dev. 54 (12) (Dec. 2007) 3393–3399, https://doi.org/10.1109/ TED.2007.908601. [10] X. Li, M.V. Hove, M. Zhao, K. Geens, V. Lempinen, J. Sormunen, G. Groeseneken, S. Decoutere, 200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration, IEEE Electron. Device Lett. 38 (7) (July 2017) 918–921, https://doi.org/10.1109/LED.2017. 2703304. [11] E.A. Jones, F. Wang, B. Ozpineci, Application-based review of GaN HFETs, Proc. 2014 IEEE Workshop Wide Bandgap Power Devices Appl, 2014, pp. 24–29. [12] X. Luo, J. Wei, X. Shi, K. Zhou, R. Tian, B. Zhang, Z. Li, Novel reduced on-resistance LDMOS with an enhanced breakdown voltage, IEEE Trans. Electron. Dev. 61 (12) (Dec. 2014) 4304–4308, https://doi.org/10.1109/TED.2014.2364842. [13] J. Du, N. Chen, P. Pan, Z. Bai, L. Li, Jianghui Mo, Qi Yu, High breakdown voltage AlGaN/GaN HEMT with high-K/low-K compound passivation, Electron. Lett. 51 (1) (Jan. 2015) 104–106, https://doi.org/10.1049/el.2014.3252. [14] J. Du, R. Li, Z. Bai, Y. Liu, Q. Yu, High breakdown voltage GaN-on-insulator based heterojunction field effect transistor with a partial back barrier layer, Superlattice. Microst. 111 (Nov. 2017) 760–766, https://doi.org/10.1016/j.spmi.2017.07.033. [15] R. Hao, W. Li, K. Fu, G. Yu, L. Song, J. Yuan, J. Li, X. Deng, X. Zhang, Q. Zhou, Y. Fan, W. Shi, Y. Cai, X. Zhang, B. Zhang, Breakdown enhancement and current collapse suppression by high-resistivity GaN cap layer in normally-off AlGaN/GaN HEMTs, IEEE Electron. Device Lett. 38 (11) (Nov. 2017) 1567–1570, https:// doi.org/10.1109/LED.2017.2749678. [16] J. Du, Z. Jiang, Z. Bai, P. Pan, Q. Yu, Design and simulation of high breakdown voltage AlGaN/GaN HEMTs with a charged passivation layer for microwave power applications, J. Comput. Electron. 16 (3) (Sep. 2017) 741–747, https://doi.org/10.1007/s10825-017-0988-5. [17] S. Gustafsson, J.T. Chen, J. Bergsten, U. Forsberg, M. Thorsell, E. Janzén, N. Rorsman, Dispersive effects in microwave AlGaN/AlN/GaN HEMTs with carbondoped buffer, IEEE Trans. Electron. Dev. 62 (7) (May 2015) 2162–2169, https://doi.org/10.1109/TED.2015.2428613. [18] Ming Tao, M. Wang, C.P. Wen, J. Wang, Y. Hao, W. Wu, K. Cheng, B. Shen, Kilovolt GaN MOSHEMT on silicon substrate with breakdown electric field close to the theoretical limit, Proc. Int. Symp. Power Semicond, May 2017, pp. 93–96, , https://doi.org/10.23919/ISPSD.2017.7988901. [19] A. Nishikawa, K. Kumakur, T. Makimoto, High critical electric field exceeding 8 MV/cm measured using an AlGaN p–i–n vertical conducting diode on n-SiC substrate, Jpn. J. Appl. Phys. 46 (4B) (2007) 2316–2319. [20] L. Su, F. Lee, J.J. Huang, Enhancement-mode GaN-based high-electron mobility transistors on the Si substrate with a P-Type GaN cap layer, IEEE Trans. Electron. Dev. 61 (2) (Feb. 2014) 460–465, https://doi.org/10.1109/TED.2013.2294337. [21] Z. Bai, J. Du, Qi Xin, R. Li, Q. Yu, Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination, Superlattice. Microst. (114) (Feb. 2018), https://doi.org/10.1016/j.spmi.2017.12.026. [22] Z. Bai, J. Du, Z. Jiang, and Q, Yu, Design of high performance normally-off dual junction gate AlGaN/GaN heterostructure field effect transistors for high voltage application, J. Comput. Electron. https://dx.doi.org.10.1007/s10825-017-1029-0. [23] Z. Bai, J. Du, Q. Xin, R. Li, and Q. Yu, Simulation design of high reverse blocking high-K/low-K compound passivation AlGaN/GaN Schottky barrier diode with gated edge termination, Superlattice. Microst. https://dx.doi.org.10.1016/j.spmi.2017.07.060. [24] T. Wu, B. Bakeroot, H. Liang, N. Posthuma, S. You, N. Ronchi, S. Stoffels, D. Marcon, S. Decoutere, Analysis of the gate capacitance–voltage characteristics in pGaN/AlGaN/GaN heterostructures, IEEE Electron. Device Lett. 38 (12) (Dec. 2017) 1696–1699, https://doi.org/10.1109/LED.2017.2768099. [25] H. Ishida, D. Shibata, M. Yanagihara, et al., Unlimited high breakdown voltage by natural super junction of polarized semiconductor, IEEE Electron. Device Lett. 29 (10) (Oct. 2008) 1087–1089, https://doi.org/10.1109/LED.2008.2002753. [26] K. Shenai, C. Cavallaro, S. Musumeci, R. Pagano, A. Raciti, Modeling low-voltage power MOSFETs as synchronous rectifiers in buck converter applications, Proc. 38th IAS Annual Meeting on Conference Record of the Industry Applications Conference, Jan. 2003, pp. 1794–1801, , https://doi.org/10.1109/IAS.2003. 1257798. [27] H. Wang, J. Wei, R. Xie, C. Liu, G. Tang, K.J. Chen, Maximizing the performance of 650-V p-GaN gate HEMTs: dynamic RON characterization and circuit design considerations, IEEE Trans. Power Electron. 32 (7) (July 2017) 5539–5549, https://doi.org/10.1109/TPEL.2016.2610460. [28] TPH3208PS Datasheet, Transphorm, Goleta, CA, USA, 2016 [Online]. Available http://www.transphormusa.com. [29] I. Hwang, H. Choi, J. Lee, H.S. Choi, J. Kim, J. Ha, C. Um, S. Hwang, Jaejoon, J. Kim, J. Shin, Y. Park, U. Chung, I. Yoo, K. Kim, 1.6kV, 2.9 mΩ cm2 Normally-off p-GaN HEMT Device, Proc. Int. Symp. Power Semicond, June 2012, pp. 41–44, , https://doi.org/10.1109/ISPSD.2012.6229018. [30] O. Hilt, A. Knauer, F. Brunner, E. Bahat-Treidel, J. Würfl, Normally-off AlGaN/GaN HFET with p-type GaN gate and AlGaN buffer, Proc. Int. Symp. Power Semicond, June 2010, pp. 347–350. [31] O. Hilt, P. Kotara, F. Brunner, A. Knauer, R. Zhytnytska, J. Würfl, Improved vertical isolation for normally-off high voltage GaN-HFETs on n-SiC substrates, IEEE Trans. Electron. Dev. 60 (10) (Oct. 2013) 3084–3090, https://doi.org/10.1109/TED.2013.2259492. [32] H. Handa, S. Ujita, D. Shibata, R. Kajitani, N. Shiozaki, M. Ogawa, H. Umeda, K. Tanaka, S. Tamura, T. Hatsuda, M. Ishida, T. Ueda, High-speed switching and current-collapse-free operation by GaN gate injection transistors with thick GaN buffer on bulk GaN substrates, Proc. IEEE International Electron Devices Meeting (IEDM), Dec. 2016, pp. 10.3.1–10.3.4, , https://doi.org/10.1109/IEDM.2016.7838387. [33] D. Ji, W. Li, S. Chowdhury, Switching performance analysis of GaN OG-FET using TCAD device-circuit-integrated model, Proc. Int. Symp. Power Semicond, May 2018, pp. 208–211.

10