Version 3 gets Xenix nearer MS-DOS

Version 3 gets Xenix nearer MS-DOS

Version 3 gets Xenix nearer MS-DOS Xenix version 3.0 has been announced by UK systems house Logica. This implementation of Microsoft's Unix system III...

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Version 3 gets Xenix nearer MS-DOS Xenix version 3.0 has been announced by UK systems house Logica. This implementation of Microsoft's Unix system III is specifically for 16-bit microcomputers. The operating system includes menus, an interface for mouse devices and an intermachine mailer. It can read from and write to MS-DOS files. There is a built-in Help function. Users can add new options of their own to the menu. Xenix 3.0 is licensed in three parts. Each is relevant to certain applications. The basic package is the timesharing system. It is required for all Xenix 3.0 implementations. It contains the system Kirk.. protecting kernel and standard functions. The software development system contains compilers, a [in ker, files, c libraries and various functions, The text processing system contains text formatters, macro packages and less commonly used functions for specific end-user applications. Networking in Xenix 3.0 is based on the Berkeley mail program. Machines are connected by the intermachine mailer viaserial lines. Commands can be entered on one machine for execution on another. Files can be transferred between machines. Logica announced its second-source agreement with Microsoft Corporation of the USA in January 1983. 'We're delighted to be associated with Microsoft,' said the director of Logica's software products group, Gordon Kirk. 'Unix has long been viewed as a complex, rather cumbersome operating system for large computers. Features such as the visual shell and mouse interface included in Xenix 3.0 protect the inexperienced user from the inner complexity.'


Mostek's 256k dRAM aimed at small systems accesses in 100 ns

Xenix 3.0 is being ported to Tycom's Microframe and Plessey's system 68. Porting to ACT's Apricot portable computer is under way. (Logico, 64

A 256k dynamic RAM with 32k x 8 architecture has been announced by Mostek in the USA. 'The Mostek 32k x 8 dynamic RAM is specifically designed for small microprocessor-based systems which do not require large amounts of solid-state memory,' says the director of volatile memory development for Mostek Corporation, Jerry Taylor. The MK4856 RAM has access times of 100 ns, according to Mostek. It is made with double-level polycrystalline and double-level metal interconnection, by a scaled NMOS process which Mostek calls LD 3 ". The memory component has nonmultiplexed addresses. This is intended to eliminate system logic and to simplify timing. An integrated refresh counter is also included. The access times of the available RAMs are specified as 100 ns, 120 ns and 150 ns. The device comes in plastic DIP IN), leadless hermetic chip carrier [E) or ceramic DIP {P) packages. The preliminary price for the N package 150 ns version in 100-piece quantities is $100. (Mostek UK Ltd, 1 Volley

Newman Street, London W1A 4SE, UK. Tel: 01-637 911 I. Telex." 27200)

Drive, Kingsbury Rood, London NW9, UK. Tel: 01-204 9322)

the inexperienced user

Generator mixes differently timed components t

A clock and controller generator has been introduced by Zilog (UK). The Z8581 is for designers who want to combine peripheral and CPU integrated circuits with different clock and timing requirements in a single system. The generator contains two independent 20 MHz oscillators, the system clock oscillator and the general purpose oscillator. These can use separate crystals or can be synchronized from other frequency sources within the system. Both have MOS drivers. Zilog says the drivers can handle capacitive loads of up to 200 pF. The system clock oscillator has an additional TTL output at source frequency. Under the control of two inputs

(ADD 1 and ADD 2) the MOS-level output of the system oscillator can be 'stretched'. This allows one, two, three or four time periods to be added to each clock cycle. The input INH inhibits the function of ADD 1 and ADD 2. The input STRH stretches the clock output for as long as it is asserted. The generator circuit is produced by Zilog's Z-4 process. This uses stepper technology to give a 2.5 jura N-channel chip whose gate delay is 1 ns, says Zilog. The Z8581 operates on +5 V DC. It comes in an 18-pin DIP. (Zilog (UK)

Ltd, Zilog House, Moorbridge Rood, Maidenhead, Berks SL6 8PL, UK. Tel: (0628) 39200. Telex: 848609)

microprocessors and microsystems